Lines Matching +full:0 +full:x37000
49 { P_XO, 0 },
68 .offset = 0x21000,
71 .enable_reg = 0x45008,
84 .offset = 0x21000,
88 .enable_reg = 0x45000,
89 .enable_mask = BIT(0),
100 .offset = 0x21000,
104 .enable_reg = 0x45000,
105 .enable_mask = BIT(0),
117 .offset = 0x20000,
120 .enable_reg = 0x45000,
134 .alpha_hi = 0x70,
135 .alpha = 0x0,
137 .post_div_mask = 0xf << 8,
138 .post_div_val = 0x1 << 8,
139 .vco_mask = 0x3 << 20,
140 .main_output_mask = 0x1,
141 .config_ctl_val = 0x4001055b,
145 { 700000000, 1400000000, 0 },
149 .offset = 0x22000,
164 .offset = 0x24000,
167 .enable_reg = 0x45000,
179 .l_reg = 0x37004,
180 .m_reg = 0x37008,
181 .n_reg = 0x3700C,
182 .config_reg = 0x37014,
183 .mode_reg = 0x37000,
184 .status_reg = 0x3701C,
195 .enable_reg = 0x45000,
208 { P_XO, 0 },
223 { P_XO, 0 },
237 { P_XO, 0 },
249 { P_XO, 0 },
259 { P_XO, 0 },
269 { P_XO, 0 },
279 { P_XO, 0 },
293 { P_XO, 0 },
303 { P_XO, 0 },
317 { P_XO, 0 },
327 { P_XO, 0 },
337 { P_XO, 0 },
347 { P_XO, 0 },
361 { P_XO, 0 },
371 { P_XO, 0 },
379 { P_XO, 0 },
389 F(19200000, P_XO, 1, 0, 0),
390 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
391 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
392 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
397 .cmd_rcgr = 0x46000,
398 .mnd_width = 0,
412 F(19200000, P_XO, 1, 0, 0),
413 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
418 .cmd_rcgr = 0x602c,
419 .mnd_width = 0,
433 F(4800000, P_XO, 4, 0, 0),
434 F(9600000, P_XO, 2, 0, 0),
436 F(19200000, P_XO, 1, 0, 0),
438 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
443 .cmd_rcgr = 0x6034,
457 .cmd_rcgr = 0x200c,
458 .mnd_width = 0,
472 F(4800000, P_XO, 4, 0, 0),
473 F(9600000, P_XO, 2, 0, 0),
476 F(19200000, P_XO, 1, 0, 0),
482 .cmd_rcgr = 0x2024,
496 .cmd_rcgr = 0x3000,
497 .mnd_width = 0,
511 F(4800000, P_XO, 4, 0, 0),
512 F(9600000, P_XO, 2, 0, 0),
515 F(19200000, P_XO, 1, 0, 0),
522 .cmd_rcgr = 0x3014,
536 .cmd_rcgr = 0x4000,
537 .mnd_width = 0,
550 .cmd_rcgr = 0x4024,
564 .cmd_rcgr = 0x5000,
565 .mnd_width = 0,
578 .cmd_rcgr = 0x5024,
596 F(19200000, P_XO, 1, 0, 0),
612 .cmd_rcgr = 0x600c,
626 .cmd_rcgr = 0x2044,
640 .cmd_rcgr = 0x3034,
654 .cmd_rcgr = 0x4014,
657 .cfg_off = 0x20,
669 .cmd_rcgr = 0xc00c,
670 .mnd_width = 0,
683 .cmd_rcgr = 0xc024,
697 .cmd_rcgr = 0xc044,
711 .cmd_rcgr = 0x4d044,
712 .mnd_width = 0,
726 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
727 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
728 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
733 .cmd_rcgr = 0x4e01c,
747 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
748 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
749 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
754 .cmd_rcgr = 0x4e014,
755 .mnd_width = 0,
768 F(19200000, P_XO, 1, 0, 0),
773 .cmd_rcgr = 0x4d05c,
774 .mnd_width = 0,
787 F(19200000, P_XO, 1, 0, 0),
788 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
789 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
790 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
791 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
792 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
793 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
794 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
795 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
796 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
797 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
798 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
799 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
800 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
801 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
802 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
807 .cmd_rcgr = 0x59000,
808 .mnd_width = 0,
821 F(19200000, P_XO, 1, 0, 0),
822 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
823 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
828 .cmd_rcgr = 0x8004,
842 .cmd_rcgr = 0x9004,
856 .cmd_rcgr = 0xa004,
870 .cmd_rcgr = 0x4d0e4,
871 .mnd_width = 0,
884 .cmd_rcgr = 0x4d0dc,
885 .mnd_width = 0,
898 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
899 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
900 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
901 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
902 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
903 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
904 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
905 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
906 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
911 .cmd_rcgr = 0x4d014,
912 .mnd_width = 0,
925 F(1200000, P_XO, 16, 0, 0),
930 .cmd_rcgr = 0x3e024,
944 F(19200000, P_XO, 1, 0, 0),
945 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
946 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
951 .cmd_rcgr = 0x3e01c,
952 .mnd_width = 0,
965 .cmd_rcgr = 0x4d000,
979 F(19200000, P_XO, 1, 0, 0),
980 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
985 .cmd_rcgr = 0x44010,
986 .mnd_width = 0,
1003 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1004 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1005 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1006 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1007 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1008 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1013 .cmd_rcgr = 0x42004,
1027 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1028 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1033 .cmd_rcgr = 0x5d000,
1051 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1052 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1053 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1054 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1059 .cmd_rcgr = 0x43004,
1073 .cmd_rcgr = 0x41048,
1074 .mnd_width = 0,
1087 F(19200000, P_XO, 1, 0, 0),
1088 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1089 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1090 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1095 .cmd_rcgr = 0x39028,
1109 .cmd_rcgr = 0x3901c,
1110 .mnd_width = 0,
1123 .cmd_rcgr = 0x3903c,
1124 .mnd_width = 0,
1137 F(19200000, P_XO, 1, 0, 0),
1138 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1139 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1140 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1141 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1146 .cmd_rcgr = 0x41010,
1147 .mnd_width = 0,
1160 .cmd_rcgr = 0x4d02c,
1161 .mnd_width = 0,
1174 F(19200000, P_XO, 1, 0, 0),
1175 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1176 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1177 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1182 .cmd_rcgr = 0x5e010,
1183 .mnd_width = 0,
1196 .halt_reg = 0x4601c,
1199 .enable_reg = 0x45004,
1214 .halt_reg = 0x5b004,
1217 .enable_reg = 0x4500c,
1227 .halt_reg = 0x59034,
1230 .enable_reg = 0x59034,
1231 .enable_mask = BIT(0),
1244 .halt_reg = 0x59030,
1247 .enable_reg = 0x59030,
1248 .enable_mask = BIT(0),
1257 .halt_reg = 0x31030,
1260 .enable_reg = 0x31030,
1261 .enable_mask = BIT(0),
1275 .halt_reg = 0x31038,
1278 .enable_reg = 0x31038,
1279 .enable_mask = BIT(0),
1288 .halt_reg = 0x1008,
1291 .enable_reg = 0x45004,
1301 .halt_reg = 0x77004,
1304 .enable_reg = 0x77004,
1305 .enable_mask = BIT(0),
1314 .halt_reg = 0x77008,
1317 .enable_reg = 0x77008,
1318 .enable_mask = BIT(0),
1327 .halt_reg = 0x6028,
1330 .enable_reg = 0x6028,
1331 .enable_mask = BIT(0),
1345 .halt_reg = 0x6024,
1348 .enable_reg = 0x6024,
1349 .enable_mask = BIT(0),
1363 .halt_reg = 0x2008,
1366 .enable_reg = 0x2008,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0x2004,
1384 .enable_reg = 0x2004,
1385 .enable_mask = BIT(0),
1399 .halt_reg = 0x3010,
1402 .enable_reg = 0x3010,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0x300c,
1420 .enable_reg = 0x300c,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0x4020,
1438 .enable_reg = 0x4020,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0x401c,
1456 .enable_reg = 0x401c,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0x5020,
1474 .enable_reg = 0x5020,
1475 .enable_mask = BIT(0),
1489 .halt_reg = 0x501c,
1492 .enable_reg = 0x501c,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0x6004,
1510 .enable_reg = 0x6004,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x203c,
1528 .enable_reg = 0x203c,
1529 .enable_mask = BIT(0),
1543 .halt_reg = 0x302c,
1546 .enable_reg = 0x302c,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0x400c,
1564 .enable_reg = 0x400c,
1565 .enable_mask = BIT(0),
1579 .halt_reg = 0xb008,
1582 .enable_reg = 0x45004,
1592 .halt_reg = 0xc008,
1595 .enable_reg = 0xc008,
1596 .enable_mask = BIT(0),
1610 .halt_reg = 0xc004,
1613 .enable_reg = 0xc004,
1614 .enable_mask = BIT(0),
1628 .halt_reg = 0xc03c,
1631 .enable_reg = 0xc03c,
1632 .enable_mask = BIT(0),
1646 .halt_reg = 0x1300c,
1649 .enable_reg = 0x45004,
1659 .halt_reg = 0x16024,
1662 .enable_reg = 0x45004,
1663 .enable_mask = BIT(0),
1672 .halt_reg = 0x16020,
1675 .enable_reg = 0x45004,
1685 .halt_reg = 0x1601c,
1688 .enable_reg = 0x45004,
1698 .halt_reg = 0x4e010,
1701 .enable_reg = 0x4e010,
1702 .enable_mask = BIT(0),
1711 .halt_reg = 0x4e004,
1714 .enable_reg = 0x4e004,
1715 .enable_mask = BIT(0),
1729 .halt_reg = 0x4e008,
1732 .enable_reg = 0x4e008,
1733 .enable_mask = BIT(0),
1747 .halt_reg = 0x4e00c,
1750 .enable_reg = 0x4e00c,
1751 .enable_mask = BIT(0),
1760 .halt_reg = 0xf008,
1763 .enable_reg = 0xf008,
1764 .enable_mask = BIT(0),
1773 .halt_reg = 0xf004,
1776 .enable_reg = 0xf004,
1777 .enable_mask = BIT(0),
1786 .halt_reg = 0x12020,
1789 .enable_reg = 0x4500C,
1799 .halt_reg = 0x12010,
1802 .enable_reg = 0x4500C,
1812 .halt_reg = 0x1203c,
1815 .enable_reg = 0x13020,
1830 .halt_reg = 0x8000,
1833 .enable_reg = 0x8000,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0x9000,
1851 .enable_reg = 0x9000,
1852 .enable_mask = BIT(0),
1866 .halt_reg = 0xa000,
1869 .enable_reg = 0xa000,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x12044,
1887 .enable_reg = 0x4500c,
1897 .halt_reg = 0x1201c,
1900 .enable_reg = 0x4500c,
1910 .halt_reg = 0x4d07c,
1913 .enable_reg = 0x4d07c,
1914 .enable_mask = BIT(0),
1923 .halt_reg = 0x4d080,
1926 .enable_reg = 0x4d080,
1927 .enable_mask = BIT(0),
1936 .halt_reg = 0x4d094,
1939 .enable_reg = 0x4d094,
1940 .enable_mask = BIT(0),
1954 .halt_reg = 0x4d098,
1957 .enable_reg = 0x4d098,
1958 .enable_mask = BIT(0),
1972 .halt_reg = 0x4d0d8,
1975 .enable_reg = 0x4d0d8,
1976 .enable_mask = BIT(0),
1990 .halt_reg = 0x4d0d4,
1993 .enable_reg = 0x4d0d4,
1994 .enable_mask = BIT(0),
2008 .halt_reg = 0x4d088,
2011 .enable_reg = 0x4d088,
2012 .enable_mask = BIT(0),
2026 .halt_reg = 0x4d084,
2029 .enable_reg = 0x4d084,
2030 .enable_mask = BIT(0),
2044 .halt_reg = 0x4d090,
2047 .enable_reg = 0x4d090,
2048 .enable_mask = BIT(0),
2062 .halt_reg = 0x59028,
2065 .enable_reg = 0x59028,
2066 .enable_mask = BIT(0),
2075 .halt_reg = 0x59020,
2078 .enable_reg = 0x59020,
2079 .enable_mask = BIT(0),
2093 .halt_reg = 0x3e014,
2096 .enable_reg = 0x45004,
2111 .halt_reg = 0x3e008,
2114 .enable_reg = 0x45004,
2124 .halt_reg = 0x3e018,
2127 .enable_reg = 0x45004,
2137 .halt_reg = 0x3e00c,
2140 .enable_reg = 0x45004,
2155 .halt_reg = 0x3e010,
2158 .enable_reg = 0x45004,
2168 .halt_reg = 0x27008,
2171 .enable_reg = 0x27008,
2172 .enable_mask = BIT(0),
2182 .halt_reg = 0x2700c,
2185 .enable_reg = 0x2700c,
2186 .enable_mask = BIT(0),
2196 .halt_reg = 0x4400c,
2199 .enable_reg = 0x4400c,
2200 .enable_mask = BIT(0),
2214 .halt_reg = 0x44004,
2217 .enable_reg = 0x44004,
2218 .enable_mask = BIT(0),
2227 .halt_reg = 0x13004,
2230 .enable_reg = 0x45004,
2241 .halt_reg = 0x44018,
2244 .enable_reg = 0x44018,
2245 .enable_mask = BIT(0),
2254 .halt_reg = 0x49004,
2257 .enable_reg = 0x49004,
2258 .enable_mask = BIT(0),
2267 .halt_reg = 0x4a004,
2270 .enable_reg = 0x4a004,
2271 .enable_mask = BIT(0),
2280 .halt_reg = 0x29084,
2283 .enable_reg = 0x45004,
2293 .halt_reg = 0x4201c,
2296 .enable_reg = 0x4201c,
2297 .enable_mask = BIT(0),
2306 .halt_reg = 0x42018,
2309 .enable_reg = 0x42018,
2310 .enable_mask = BIT(0),
2324 .halt_reg = 0x5d014,
2327 .enable_reg = 0x5d014,
2328 .enable_mask = BIT(0),
2342 .halt_reg = 0x5e004,
2345 .enable_reg = 0x5e004,
2346 .enable_mask = BIT(0),
2355 .halt_reg = 0x4301c,
2358 .enable_reg = 0x4301c,
2359 .enable_mask = BIT(0),
2368 .halt_reg = 0x43018,
2371 .enable_reg = 0x43018,
2372 .enable_mask = BIT(0),
2386 .halt_reg = 0x12038,
2389 .enable_reg = 0x3600C,
2399 .halt_reg = 0x26014,
2402 .enable_reg = 0x26014,
2403 .enable_mask = BIT(0),
2416 .halt_reg = 0x4100C,
2419 .enable_reg = 0x4100C,
2420 .enable_mask = BIT(0),
2429 .halt_reg = 0x41044,
2432 .enable_reg = 0x41044,
2433 .enable_mask = BIT(0),
2447 .halt_reg = 0x4102c,
2450 .enable_reg = 0x4102c,
2451 .enable_mask = BIT(0),
2460 .halt_reg = 0x3900c,
2463 .enable_reg = 0x3900c,
2464 .enable_mask = BIT(0),
2478 .halt_reg = 0x39014,
2481 .enable_reg = 0x39014,
2482 .enable_mask = BIT(0),
2496 .halt_reg = 0x39010,
2499 .enable_reg = 0x39010,
2500 .enable_mask = BIT(0),
2509 .halt_reg = 0x39044,
2512 .enable_reg = 0x39044,
2513 .enable_mask = BIT(0),
2529 .enable_reg = 0x39018,
2530 .enable_mask = BIT(0),
2539 .halt_reg = 0x41030,
2542 .enable_reg = 0x41030,
2543 .enable_mask = BIT(0),
2552 .halt_reg = 0x41004,
2555 .enable_reg = 0x41004,
2556 .enable_mask = BIT(0),
2570 .halt_reg = 0x1e004,
2573 .enable_reg = 0x1e004,
2574 .enable_mask = BIT(0),
2583 .halt_reg = 0x1e008,
2586 .enable_reg = 0x1e008,
2587 .enable_mask = BIT(0),
2596 .gdscr = 0x4d078,
2604 .gdscr = 0x5901c,
2767 [GCC_GENI_IR_BCR] = { 0x0F000 },
2768 [GCC_CDSP_RESTART] = { 0x18000 },
2769 [GCC_USB_HS_BCR] = { 0x41000 },
2770 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2771 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2772 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2773 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2774 [GCC_USB3_PHY_BCR] = { 0x39004 },
2775 [GCC_USB_30_BCR] = { 0x39000 },
2776 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2777 [GCC_PCIE_0_BCR] = { 0x3e000 },
2778 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2779 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2780 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2781 [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2782 [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2783 [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2784 [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2785 [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2786 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2787 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2788 [GCC_EMAC_BCR] = { 0x4e000 },
2789 [GCC_WDSP_RESTART] = {0x19000},
2796 .max_register = 0x7f000,