Lines Matching +full:0 +full:x37000
53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
86 .n_reg = 0x2000c,
87 .config_reg = 0x20010,
88 .mode_reg = 0x20000,
89 .status_reg = 0x2001c,
102 .enable_reg = 0x45000,
115 .l_reg = 0x4a004,
116 .m_reg = 0x4a008,
117 .n_reg = 0x4a00c,
118 .config_reg = 0x4a010,
119 .mode_reg = 0x4a000,
120 .status_reg = 0x4a01c,
133 .enable_reg = 0x45000,
146 .l_reg = 0x23004,
147 .m_reg = 0x23008,
148 .n_reg = 0x2300c,
149 .config_reg = 0x23010,
150 .mode_reg = 0x23000,
151 .status_reg = 0x2301c,
164 .enable_reg = 0x45000,
177 .l_reg = 0x22004,
178 .m_reg = 0x22008,
179 .n_reg = 0x2200c,
180 .config_reg = 0x22010,
181 .mode_reg = 0x22000,
182 .status_reg = 0x2201c,
195 .enable_reg = 0x45000,
212 .vco_val = 0x0,
214 .pre_div_val = 0x0,
216 .post_div_val = 0x0,
219 .main_output_mask = BIT(0),
224 .l_reg = 0x24004,
225 .m_reg = 0x24008,
226 .n_reg = 0x2400c,
227 .config_reg = 0x24010,
228 .mode_reg = 0x24000,
229 .status_reg = 0x2401c,
242 .enable_reg = 0x45000,
259 .vco_val = 0x0,
261 .pre_div_val = 0x0,
263 .post_div_val = 0x0,
266 .main_output_mask = BIT(0),
270 .l_reg = 0x25004,
271 .m_reg = 0x25008,
272 .n_reg = 0x2500c,
273 .config_reg = 0x25010,
274 .mode_reg = 0x25000,
275 .status_reg = 0x2501c,
288 .enable_reg = 0x45000,
301 .l_reg = 0x37004,
302 .m_reg = 0x37008,
303 .n_reg = 0x3700c,
304 .config_reg = 0x37010,
305 .mode_reg = 0x37000,
306 .status_reg = 0x3701c,
319 .enable_reg = 0x45000,
332 { P_XO, 0 },
342 { P_XO, 0 },
354 { P_XO, 0 },
366 { P_XO, 0 },
382 { P_XO, 0 },
394 { P_XO, 0 },
408 { P_XO, 0 },
418 { P_XO, 0 },
432 { P_XO, 0 },
448 { P_XO, 0 },
460 { P_XO, 0, },
470 { P_XO, 0 },
482 { P_XO, 0 },
500 { P_XO, 0 },
512 { P_XO, 0 },
528 { P_XO, 0 },
542 { P_XO, 0 },
558 { P_XO, 0 },
574 { P_XO, 0 },
584 { P_XO, 0 },
610 .cmd_rcgr = 0x27000,
622 .cmd_rcgr = 0x26004,
634 .cmd_rcgr = 0x32024,
647 .cmd_rcgr = 0x2600c,
660 F(80000000, P_GPLL0, 10, 0, 0),
665 .cmd_rcgr = 0x5a000,
679 F(19200000, P_XO, 1, 0, 0),
680 F(50000000, P_GPLL0, 16, 0, 0),
681 F(100000000, P_GPLL0, 8, 0, 0),
682 F(133330000, P_GPLL0, 6, 0, 0),
687 .cmd_rcgr = 0x46000,
700 F(100000000, P_GPLL0, 8, 0, 0),
701 F(200000000, P_GPLL0, 4, 0, 0),
706 .cmd_rcgr = 0x4e020,
719 .cmd_rcgr = 0x4f020,
732 F(19200000, P_XO, 1, 0, 0),
733 F(50000000, P_GPLL0, 16, 0, 0),
734 F(80000000, P_GPLL0, 10, 0, 0),
735 F(100000000, P_GPLL0, 8, 0, 0),
736 F(160000000, P_GPLL0, 5, 0, 0),
737 F(200000000, P_GPLL0, 4, 0, 0),
738 F(220000000, P_GPLL3, 5, 0, 0),
739 F(266670000, P_GPLL0, 3, 0, 0),
740 F(310000000, P_GPLL2_AUX, 3, 0, 0),
741 F(400000000, P_GPLL0, 2, 0, 0),
742 F(465000000, P_GPLL2_AUX, 2, 0, 0),
743 F(550000000, P_GPLL3, 2, 0, 0),
748 .cmd_rcgr = 0x59000,
761 F(50000000, P_GPLL0, 16, 0, 0),
762 F(80000000, P_GPLL0, 10, 0, 0),
763 F(100000000, P_GPLL0, 8, 0, 0),
764 F(160000000, P_GPLL0, 5, 0, 0),
765 F(177780000, P_GPLL0, 4.5, 0, 0),
766 F(200000000, P_GPLL0, 4, 0, 0),
767 F(266670000, P_GPLL0, 3, 0, 0),
768 F(320000000, P_GPLL0, 2.5, 0, 0),
769 F(400000000, P_GPLL0, 2, 0, 0),
770 F(465000000, P_GPLL2, 2, 0, 0),
771 F(480000000, P_GPLL4, 2.5, 0, 0),
772 F(600000000, P_GPLL4, 2, 0, 0),
777 .cmd_rcgr = 0x58000,
790 F(19200000, P_XO, 1, 0, 0),
791 F(50000000, P_GPLL0, 16, 0, 0),
796 .cmd_rcgr = 0x0200c,
810 F(4800000, P_XO, 4, 0, 0),
811 F(9600000, P_XO, 2, 0, 0),
813 F(19200000, P_XO, 1, 0, 0),
815 F(50000000, P_GPLL0, 16, 0, 0),
820 .cmd_rcgr = 0x02024,
834 .cmd_rcgr = 0x03000,
847 .cmd_rcgr = 0x03014,
861 .cmd_rcgr = 0x04000,
874 .cmd_rcgr = 0x04024,
888 .cmd_rcgr = 0x05000,
901 .cmd_rcgr = 0x05024,
915 .cmd_rcgr = 0x06000,
928 .cmd_rcgr = 0x06024,
942 .cmd_rcgr = 0x07000,
955 .cmd_rcgr = 0x07024,
973 F(19200000, P_XO, 1, 0, 0),
988 .cmd_rcgr = 0x02044,
1002 .cmd_rcgr = 0x03034,
1016 F(19200000, P_XO, 1, 0, 0),
1022 .cmd_rcgr = 0x51000,
1049 F(100000000, P_GPLL0, 8, 0, 0),
1050 F(200000000, P_GPLL0, 4, 0, 0),
1055 .cmd_rcgr = 0x54000,
1069 .cmd_rcgr = 0x55000,
1083 F(133330000, P_GPLL0, 6, 0, 0),
1084 F(266670000, P_GPLL0, 3, 0, 0),
1085 F(320000000, P_GPLL0, 2.5, 0, 0),
1090 .cmd_rcgr = 0x57000,
1104 F(66670000, P_GPLL0, 12, 0, 0),
1109 .cmd_rcgr = 0x52000,
1123 .cmd_rcgr = 0x53000,
1137 F(100000000, P_GPLL0, 8, 0, 0),
1138 F(200000000, P_GPLL0, 4, 0, 0),
1143 .cmd_rcgr = 0x4e000,
1156 .cmd_rcgr = 0x4f000,
1169 F(160000000, P_GPLL0, 5, 0, 0),
1170 F(200000000, P_GPLL0, 4, 0, 0),
1171 F(228570000, P_GPLL0, 3.5, 0, 0),
1172 F(266670000, P_GPLL0, 3, 0, 0),
1173 F(320000000, P_GPLL0, 2.5, 0, 0),
1174 F(465000000, P_GPLL2, 2, 0, 0),
1179 .cmd_rcgr = 0x58018,
1192 F(50000000, P_GPLL0, 16, 0, 0),
1193 F(80000000, P_GPLL0, 10, 0, 0),
1194 F(100000000, P_GPLL0, 8, 0, 0),
1195 F(160000000, P_GPLL0, 5, 0, 0),
1201 .cmd_rcgr = 0x16004,
1236 F(19200000, P_XO, 1, 0, 0),
1241 .cmd_rcgr = 0x08004,
1255 .cmd_rcgr = 0x09004,
1269 .cmd_rcgr = 0x0a004,
1283 .cmd_rcgr = 0x4d044,
1296 .cmd_rcgr = 0x4d0b0,
1309 F(19200000, P_XO, 1, 0, 0),
1314 .cmd_rcgr = 0x4d060,
1327 .cmd_rcgr = 0x4d0a8,
1340 F(50000000, P_GPLL0_AUX, 16, 0, 0),
1341 F(80000000, P_GPLL0_AUX, 10, 0, 0),
1342 F(100000000, P_GPLL0_AUX, 8, 0, 0),
1343 F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1344 F(153600000, P_GPLL0, 4, 0, 0),
1345 F(160000000, P_GPLL0_AUX, 5, 0, 0),
1346 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1347 F(200000000, P_GPLL0_AUX, 4, 0, 0),
1348 F(266670000, P_GPLL0_AUX, 3, 0, 0),
1349 F(307200000, P_GPLL1, 2, 0, 0),
1350 F(366670000, P_GPLL3_AUX, 3, 0, 0),
1355 .cmd_rcgr = 0x4d014,
1368 .cmd_rcgr = 0x4d000,
1382 .cmd_rcgr = 0x4d0b8,
1396 F(19200000, P_XO, 1, 0, 0),
1401 .cmd_rcgr = 0x4d02c,
1414 F(64000000, P_GPLL0, 12.5, 0, 0),
1420 .cmd_rcgr = 0x44010,
1437 F(50000000, P_GPLL0, 16, 0, 0),
1438 F(100000000, P_GPLL0, 8, 0, 0),
1439 F(177770000, P_GPLL0, 4.5, 0, 0),
1440 F(200000000, P_GPLL0, 4, 0, 0),
1445 .cmd_rcgr = 0x42004,
1459 .cmd_rcgr = 0x43004,
1473 F(154285000, P_GPLL6, 7, 0, 0),
1474 F(320000000, P_GPLL0, 2.5, 0, 0),
1475 F(400000000, P_GPLL0, 2, 0, 0),
1480 .cmd_rcgr = 0x1207c,
1493 F(19200000, P_XO, 1, 0, 0),
1494 F(100000000, P_GPLL0, 8, 0, 0),
1495 F(200000000, P_GPLL0, 4, 0, 0),
1496 F(266500000, P_BIMC, 4, 0, 0),
1497 F(400000000, P_GPLL0, 2, 0, 0),
1498 F(533000000, P_BIMC, 2, 0, 0),
1503 .cmd_rcgr = 0x31028,
1517 F(57140000, P_GPLL0, 14, 0, 0),
1518 F(80000000, P_GPLL0, 10, 0, 0),
1519 F(100000000, P_GPLL0, 8, 0, 0),
1524 .cmd_rcgr = 0x41010,
1537 F(64000000, P_GPLL0, 12.5, 0, 0),
1542 .cmd_rcgr = 0x3f010,
1560 .cmd_rcgr = 0x3f034,
1573 F(3200000, P_XO, 6, 0, 0),
1574 F(6400000, P_XO, 3, 0, 0),
1575 F(9600000, P_XO, 2, 0, 0),
1576 F(19200000, P_XO, 1, 0, 0),
1578 F(66670000, P_GPLL0, 12, 0, 0),
1579 F(80000000, P_GPLL0, 10, 0, 0),
1580 F(100000000, P_GPLL0, 8, 0, 0),
1585 .cmd_rcgr = 0x1c010,
1599 .halt_reg = 0x1c028,
1601 .enable_reg = 0x1c028,
1602 .enable_mask = BIT(0),
1616 .halt_reg = 0x1c024,
1618 .enable_reg = 0x1c024,
1619 .enable_mask = BIT(0),
1645 F(1600000, P_XO, 12, 0, 0),
1649 F(2400000, P_XO, 8, 0, 0),
1653 F(4800000, P_XO, 4, 0, 0),
1657 F(9600000, P_XO, 2, 0, 0),
1664 .cmd_rcgr = 0x1c054,
1678 .halt_reg = 0x1c068,
1680 .enable_reg = 0x1c068,
1681 .enable_mask = BIT(0),
1695 .cmd_rcgr = 0x1c06c,
1709 .halt_reg = 0x1c080,
1711 .enable_reg = 0x1c080,
1712 .enable_mask = BIT(0),
1726 .cmd_rcgr = 0x1c084,
1740 .halt_reg = 0x1c098,
1742 .enable_reg = 0x1c098,
1743 .enable_mask = BIT(0),
1757 F(19200000, P_XO, 1, 0, 0),
1762 .cmd_rcgr = 0x1c034,
1775 .halt_reg = 0x1c04c,
1777 .enable_reg = 0x1c04c,
1778 .enable_mask = BIT(0),
1792 .halt_reg = 0x1c050,
1794 .enable_reg = 0x1c050,
1795 .enable_mask = BIT(0),
1809 F(9600000, P_XO, 2, 0, 0),
1811 F(19200000, P_XO, 1, 0, 0),
1812 F(11289600, P_EXT_MCLK, 1, 0, 0),
1817 .cmd_rcgr = 0x1c09c,
1831 .halt_reg = 0x1c0b0,
1833 .enable_reg = 0x1c0b0,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0x1c000,
1850 .enable_reg = 0x1c000,
1851 .enable_mask = BIT(0),
1864 .halt_reg = 0x1c004,
1866 .enable_reg = 0x1c004,
1867 .enable_mask = BIT(0),
1880 F(133330000, P_GPLL0, 6, 0, 0),
1881 F(200000000, P_GPLL0, 4, 0, 0),
1882 F(266670000, P_GPLL0, 3, 0, 0),
1887 .cmd_rcgr = 0x4C000,
1901 .halt_reg = 0x01008,
1904 .enable_reg = 0x45004,
1918 .halt_reg = 0x01004,
1920 .enable_reg = 0x01004,
1921 .enable_mask = BIT(0),
1930 .halt_reg = 0x02008,
1932 .enable_reg = 0x02008,
1933 .enable_mask = BIT(0),
1947 .halt_reg = 0x02004,
1949 .enable_reg = 0x02004,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x03010,
1966 .enable_reg = 0x03010,
1967 .enable_mask = BIT(0),
1981 .halt_reg = 0x0300c,
1983 .enable_reg = 0x0300c,
1984 .enable_mask = BIT(0),
1998 .halt_reg = 0x04020,
2000 .enable_reg = 0x04020,
2001 .enable_mask = BIT(0),
2015 .halt_reg = 0x0401c,
2017 .enable_reg = 0x0401c,
2018 .enable_mask = BIT(0),
2032 .halt_reg = 0x05020,
2034 .enable_reg = 0x05020,
2035 .enable_mask = BIT(0),
2049 .halt_reg = 0x0501c,
2051 .enable_reg = 0x0501c,
2052 .enable_mask = BIT(0),
2066 .halt_reg = 0x06020,
2068 .enable_reg = 0x06020,
2069 .enable_mask = BIT(0),
2083 .halt_reg = 0x0601c,
2085 .enable_reg = 0x0601c,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x07020,
2102 .enable_reg = 0x07020,
2103 .enable_mask = BIT(0),
2117 .halt_reg = 0x0701c,
2119 .enable_reg = 0x0701c,
2120 .enable_mask = BIT(0),
2134 .halt_reg = 0x0203c,
2136 .enable_reg = 0x0203c,
2137 .enable_mask = BIT(0),
2151 .halt_reg = 0x0302c,
2153 .enable_reg = 0x0302c,
2154 .enable_mask = BIT(0),
2168 .halt_reg = 0x1300c,
2171 .enable_reg = 0x45004,
2185 .halt_reg = 0x5101c,
2187 .enable_reg = 0x5101c,
2188 .enable_mask = BIT(0),
2202 .halt_reg = 0x51018,
2204 .enable_reg = 0x51018,
2205 .enable_mask = BIT(0),
2219 .halt_reg = 0x4e040,
2221 .enable_reg = 0x4e040,
2222 .enable_mask = BIT(0),
2236 .halt_reg = 0x4e03c,
2238 .enable_reg = 0x4e03c,
2239 .enable_mask = BIT(0),
2253 .halt_reg = 0x4e048,
2255 .enable_reg = 0x4e048,
2256 .enable_mask = BIT(0),
2270 .halt_reg = 0x4e058,
2272 .enable_reg = 0x4e058,
2273 .enable_mask = BIT(0),
2287 .halt_reg = 0x4e050,
2289 .enable_reg = 0x4e050,
2290 .enable_mask = BIT(0),
2304 .halt_reg = 0x4f040,
2306 .enable_reg = 0x4f040,
2307 .enable_mask = BIT(0),
2321 .halt_reg = 0x4f03c,
2323 .enable_reg = 0x4f03c,
2324 .enable_mask = BIT(0),
2338 .halt_reg = 0x4f048,
2340 .enable_reg = 0x4f048,
2341 .enable_mask = BIT(0),
2355 .halt_reg = 0x4f058,
2357 .enable_reg = 0x4f058,
2358 .enable_mask = BIT(0),
2372 .halt_reg = 0x4f050,
2374 .enable_reg = 0x4f050,
2375 .enable_mask = BIT(0),
2389 .halt_reg = 0x58050,
2391 .enable_reg = 0x58050,
2392 .enable_mask = BIT(0),
2406 .halt_reg = 0x54018,
2408 .enable_reg = 0x54018,
2409 .enable_mask = BIT(0),
2423 .halt_reg = 0x55018,
2425 .enable_reg = 0x55018,
2426 .enable_mask = BIT(0),
2440 .halt_reg = 0x50004,
2442 .enable_reg = 0x50004,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0x57020,
2459 .enable_reg = 0x57020,
2460 .enable_mask = BIT(0),
2474 .halt_reg = 0x57024,
2476 .enable_reg = 0x57024,
2477 .enable_mask = BIT(0),
2491 .halt_reg = 0x57028,
2493 .enable_reg = 0x57028,
2494 .enable_mask = BIT(0),
2508 .halt_reg = 0x52018,
2510 .enable_reg = 0x52018,
2511 .enable_mask = BIT(0),
2525 .halt_reg = 0x53018,
2527 .enable_reg = 0x53018,
2528 .enable_mask = BIT(0),
2542 .halt_reg = 0x5600c,
2544 .enable_reg = 0x5600c,
2545 .enable_mask = BIT(0),
2559 .halt_reg = 0x4e01c,
2561 .enable_reg = 0x4e01c,
2562 .enable_mask = BIT(0),
2576 .halt_reg = 0x4f01c,
2578 .enable_reg = 0x4f01c,
2579 .enable_mask = BIT(0),
2593 .halt_reg = 0x5a014,
2595 .enable_reg = 0x5a014,
2596 .enable_mask = BIT(0),
2610 .halt_reg = 0x56004,
2612 .enable_reg = 0x56004,
2613 .enable_mask = BIT(0),
2627 .halt_reg = 0x58040,
2629 .enable_reg = 0x58040,
2630 .enable_mask = BIT(0),
2644 .halt_reg = 0x5803c,
2646 .enable_reg = 0x5803c,
2647 .enable_mask = BIT(0),
2661 .halt_reg = 0x58038,
2663 .enable_reg = 0x58038,
2664 .enable_mask = BIT(0),
2678 .halt_reg = 0x58044,
2680 .enable_reg = 0x58044,
2681 .enable_mask = BIT(0),
2695 .halt_reg = 0x58048,
2697 .enable_reg = 0x58048,
2698 .enable_mask = BIT(0),
2712 .halt_reg = 0x16024,
2715 .enable_reg = 0x45004,
2716 .enable_mask = BIT(0),
2730 .halt_reg = 0x16020,
2733 .enable_reg = 0x45004,
2748 .halt_reg = 0x1601c,
2751 .enable_reg = 0x45004,
2766 .halt_reg = 0x59024,
2768 .enable_reg = 0x59024,
2769 .enable_mask = BIT(0),
2783 .halt_reg = 0x08000,
2785 .enable_reg = 0x08000,
2786 .enable_mask = BIT(0),
2800 .halt_reg = 0x09000,
2802 .enable_reg = 0x09000,
2803 .enable_mask = BIT(0),
2817 .halt_reg = 0x0a000,
2819 .enable_reg = 0x0a000,
2820 .enable_mask = BIT(0),
2834 .halt_reg = 0x4d07c,
2836 .enable_reg = 0x4d07c,
2837 .enable_mask = BIT(0),
2851 .halt_reg = 0x4d080,
2853 .enable_reg = 0x4d080,
2854 .enable_mask = BIT(0),
2868 .halt_reg = 0x4d094,
2870 .enable_reg = 0x4d094,
2871 .enable_mask = BIT(0),
2885 .halt_reg = 0x4d0a0,
2887 .enable_reg = 0x4d0a0,
2888 .enable_mask = BIT(0),
2902 .halt_reg = 0x4d098,
2904 .enable_reg = 0x4d098,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x4d09c,
2921 .enable_reg = 0x4d09c,
2922 .enable_mask = BIT(0),
2936 .halt_reg = 0x4D088,
2938 .enable_reg = 0x4D088,
2939 .enable_mask = BIT(0),
2953 .halt_reg = 0x4d084,
2955 .enable_reg = 0x4d084,
2956 .enable_mask = BIT(0),
2970 .halt_reg = 0x4d0a4,
2972 .enable_reg = 0x4d0a4,
2973 .enable_mask = BIT(0),
2987 .halt_reg = 0x4d090,
2989 .enable_reg = 0x4d090,
2990 .enable_mask = BIT(0),
3004 .halt_reg = 0x49000,
3006 .enable_reg = 0x49000,
3007 .enable_mask = BIT(0),
3021 .halt_reg = 0x49004,
3023 .enable_reg = 0x49004,
3024 .enable_mask = BIT(0),
3038 .halt_reg = 0x59028,
3040 .enable_reg = 0x59028,
3041 .enable_mask = BIT(0),
3055 .halt_reg = 0x59020,
3057 .enable_reg = 0x59020,
3058 .enable_mask = BIT(0),
3072 .halt_reg = 0x4400c,
3074 .enable_reg = 0x4400c,
3075 .enable_mask = BIT(0),
3089 .halt_reg = 0x44004,
3091 .enable_reg = 0x44004,
3092 .enable_mask = BIT(0),
3106 .halt_reg = 0x13004,
3109 .enable_reg = 0x45004,
3123 .halt_reg = 0x4201c,
3125 .enable_reg = 0x4201c,
3126 .enable_mask = BIT(0),
3140 .halt_reg = 0x42018,
3142 .enable_reg = 0x42018,
3143 .enable_mask = BIT(0),
3157 .halt_reg = 0x4301c,
3159 .enable_reg = 0x4301c,
3160 .enable_mask = BIT(0),
3174 .halt_reg = 0x43018,
3176 .enable_reg = 0x43018,
3177 .enable_mask = BIT(0),
3191 .halt_reg = 0x12018,
3194 .enable_reg = 0x4500c,
3208 .halt_reg = 0x12020,
3211 .enable_reg = 0x4500c,
3225 .halt_reg = 0x12010,
3228 .enable_reg = 0x4500c,
3242 .halt_reg = 0x1201c,
3245 .enable_reg = 0x4500c,
3260 .halt_reg = 0x12014,
3263 .enable_reg = 0x4500c,
3278 .halt_reg = 0x1203c,
3281 .enable_reg = 0x4500c,
3296 .halt_reg = 0x12034,
3299 .enable_reg = 0x4500c,
3314 .halt_reg = 0x12038,
3317 .enable_reg = 0x4500c,
3332 .halt_reg = 0x12044,
3335 .enable_reg = 0x4500c,
3350 .halt_reg = 0x12040,
3353 .enable_reg = 0x4500c,
3368 .halt_reg = 0x1201c,
3371 .enable_reg = 0x4500c,
3386 .halt_reg = 0x31024,
3388 .enable_reg = 0x31024,
3389 .enable_mask = BIT(0),
3403 .halt_reg = 0x31040,
3405 .enable_reg = 0x31040,
3406 .enable_mask = BIT(0),
3420 .halt_reg = 0x4102c,
3422 .enable_reg = 0x4102c,
3423 .enable_mask = BIT(0),
3432 .halt_reg = 0x3f008,
3434 .enable_reg = 0x3f008,
3435 .enable_mask = BIT(0),
3449 .halt_reg = 0x3f030,
3451 .enable_reg = 0x3f030,
3452 .enable_mask = BIT(0),
3466 .halt_reg = 0x3f004,
3468 .enable_reg = 0x3f004,
3469 .enable_mask = BIT(0),
3483 .halt_reg = 0x41008,
3485 .enable_reg = 0x41008,
3486 .enable_mask = BIT(0),
3500 .halt_reg = 0x41004,
3502 .enable_reg = 0x41004,
3503 .enable_mask = BIT(0),
3517 .halt_reg = 0x4c020,
3519 .enable_reg = 0x4c020,
3520 .enable_mask = BIT(0),
3534 .halt_reg = 0x4c024,
3536 .enable_reg = 0x4c024,
3537 .enable_mask = BIT(0),
3551 .halt_reg = 0x4c01c,
3553 .enable_reg = 0x4c01c,
3554 .enable_mask = BIT(0),
3568 .halt_reg = 0x4c02c,
3570 .enable_reg = 0x4c02c,
3571 .enable_mask = BIT(0),
3585 .halt_reg = 0x4c034,
3587 .enable_reg = 0x4c034,
3588 .enable_mask = BIT(0),
3602 .halt_reg = 0x59040,
3604 .enable_reg = 0x59040,
3605 .enable_mask = BIT(0),
3614 .gdscr = 0x4c018,
3622 .gdscr = 0x4d078,
3630 .gdscr = 0x5701c,
3638 .gdscr = 0x58034,
3646 .gdscr = 0x5901c,
3654 .gdscr = 0x4c028,
3662 .gdscr = 0x4c030,
3870 [GCC_BLSP1_BCR] = { 0x01000 },
3871 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3872 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3873 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3874 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3875 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3876 [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3877 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3878 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3879 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3880 [GCC_IMEM_BCR] = { 0x0e000 },
3881 [GCC_SMMU_BCR] = { 0x12000 },
3882 [GCC_APSS_TCU_BCR] = { 0x12050 },
3883 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3884 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3885 [GCC_PRNG_BCR] = { 0x13000 },
3886 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3887 [GCC_CRYPTO_BCR] = { 0x16000 },
3888 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3889 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3890 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3891 [GCC_DEHR_BCR] = { 0x1f000 },
3892 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3893 [GCC_PCNOC_BCR] = { 0x27018 },
3894 [GCC_TCSR_BCR] = { 0x28000 },
3895 [GCC_QDSS_BCR] = { 0x29000 },
3896 [GCC_DCD_BCR] = { 0x2a000 },
3897 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3898 [GCC_MPM_BCR] = { 0x2c000 },
3899 [GCC_SPMI_BCR] = { 0x2e000 },
3900 [GCC_SPDM_BCR] = { 0x2f000 },
3901 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3902 [GCC_BIMC_BCR] = { 0x31000 },
3903 [GCC_RBCPR_BCR] = { 0x33000 },
3904 [GCC_TLMM_BCR] = { 0x34000 },
3905 [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3906 [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3907 [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3908 [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3909 [GCC_USB_FS_BCR] = { 0x3f000 },
3910 [GCC_USB_HS_BCR] = { 0x41000 },
3911 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3912 [GCC_SDCC1_BCR] = { 0x42000 },
3913 [GCC_SDCC2_BCR] = { 0x43000 },
3914 [GCC_PDM_BCR] = { 0x44000 },
3915 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3916 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3917 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3918 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3919 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3920 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3921 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3922 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3923 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3924 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3925 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3926 [GCC_MMSS_BCR] = { 0x4b000 },
3927 [GCC_VENUS0_BCR] = { 0x4c014 },
3928 [GCC_MDSS_BCR] = { 0x4d074 },
3929 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3930 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3931 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3932 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3933 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3934 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3935 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3936 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3937 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3938 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3939 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3940 [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3941 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3942 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3943 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3944 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3945 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3946 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3947 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3948 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3949 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3950 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3951 [GCC_OXILI_BCR] = { 0x59018 },
3952 [GCC_GMEM_BCR] = { 0x5902c },
3953 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3954 [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3955 [GCC_MDP_TBU_BCR] = { 0x62000 },
3956 [GCC_GFX_TBU_BCR] = { 0x63000 },
3957 [GCC_GFX_TCU_BCR] = { 0x64000 },
3958 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3959 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3960 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3961 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3962 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3963 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3964 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3965 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3966 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3967 [GCC_CPP_TBU_BCR] = { 0x6e000 },
3968 [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3969 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3976 .max_register = 0x80000,