Lines Matching +full:0 +full:x33000
55 { P_XO, 0 },
67 .offset = 0x20000,
70 .enable_reg = 0x0b000,
71 .enable_mask = BIT(0),
95 .offset = 0x20000,
109 .offset = 0x22000,
112 .enable_reg = 0x0b000,
124 .offset = 0x22000,
138 .offset = 0x21000,
141 .enable_reg = 0x0b000,
153 .offset = 0x21000,
167 .halt_reg = 0x3400c,
169 .enable_reg = 0x3400c,
188 { P_XO, 0 },
199 { P_XO, 0 },
210 { P_XO, 0 },
223 { P_XO, 0 },
237 { P_XO, 0 },
250 { P_XO, 0 },
263 { P_XO, 0 },
279 { P_XO, 0 },
292 { P_XO, 0 },
306 { P_XO, 0 },
318 { P_USB3PHY_0_PIPE, 0 },
331 { P_XO, 0 },
345 { P_XO, 0 },
359 { P_XO, 0 },
372 { P_XO, 0 },
386 { P_XO, 0 },
401 { P_XO, 0 },
408 F(24000000, P_XO, 1, 0, 0),
409 F(50000000, P_GPLL0, 16, 0, 0),
410 F(100000000, P_GPLL0, 8, 0, 0),
415 .cmd_rcgr = 0x2400c,
428 F(533000000, P_GPLL0, 1.5, 0, 0),
433 .cmd_rcgr = 0x24004,
446 F(9600000, P_XO, 2.5, 0, 0),
447 F(24000000, P_XO, 1, 0, 0),
448 F(50000000, P_GPLL0, 16, 0, 0),
453 .cmd_rcgr = 0x02018,
467 F(4800000, P_XO, 5, 0, 0),
470 F(24000000, P_XO, 1, 0, 0),
472 F(50000000, P_GPLL0, 16, 0, 0),
477 .cmd_rcgr = 0x02004,
491 .cmd_rcgr = 0x03018,
504 .cmd_rcgr = 0x03004,
518 .cmd_rcgr = 0x04018,
531 .cmd_rcgr = 0x04004,
545 .cmd_rcgr = 0x05018,
558 .cmd_rcgr = 0x05004,
572 .cmd_rcgr = 0x06018,
585 .cmd_rcgr = 0x06004,
599 .cmd_rcgr = 0x07018,
612 .cmd_rcgr = 0x07004,
629 F(24000000, P_XO, 1, 0, 0),
639 F(64000000, P_GPLL0, 12.5, 0, 0),
644 .cmd_rcgr = 0x0202c,
658 .cmd_rcgr = 0x0302c,
672 .cmd_rcgr = 0x0402c,
686 .cmd_rcgr = 0x0502c,
700 .cmd_rcgr = 0x0602c,
714 .cmd_rcgr = 0x0702c,
728 F(160000000, P_GPLL0, 5, 0, 0),
733 .cmd_rcgr = 0x16004,
746 .halt_reg = 0x1600c,
749 .enable_reg = 0x0b004,
763 .halt_reg = 0x24018,
766 .enable_reg = 0x0b004,
767 .enable_mask = BIT(0),
781 .halt_reg = 0x2401c,
784 .enable_reg = 0x0b004,
799 .halt_reg = 0x2024,
801 .enable_reg = 0x2024,
802 .enable_mask = BIT(0),
816 .halt_reg = 0x02020,
818 .enable_reg = 0x02020,
819 .enable_mask = BIT(0),
833 .halt_reg = 0x03024,
835 .enable_reg = 0x03024,
836 .enable_mask = BIT(0),
850 .halt_reg = 0x03020,
852 .enable_reg = 0x03020,
853 .enable_mask = BIT(0),
867 .halt_reg = 0x04024,
869 .enable_reg = 0x04024,
870 .enable_mask = BIT(0),
884 .halt_reg = 0x04020,
886 .enable_reg = 0x04020,
887 .enable_mask = BIT(0),
901 .halt_reg = 0x05024,
903 .enable_reg = 0x05024,
904 .enable_mask = BIT(0),
918 .halt_reg = 0x05020,
920 .enable_reg = 0x05020,
921 .enable_mask = BIT(0),
935 .halt_reg = 0x06024,
937 .enable_reg = 0x06024,
938 .enable_mask = BIT(0),
952 .halt_reg = 0x06020,
954 .enable_reg = 0x06020,
955 .enable_mask = BIT(0),
969 .halt_reg = 0x07024,
971 .enable_reg = 0x07024,
972 .enable_mask = BIT(0),
986 .halt_reg = 0x07020,
988 .enable_reg = 0x07020,
989 .enable_mask = BIT(0),
1003 .halt_reg = 0x02040,
1005 .enable_reg = 0x02040,
1006 .enable_mask = BIT(0),
1020 .halt_reg = 0x03040,
1022 .enable_reg = 0x03040,
1023 .enable_mask = BIT(0),
1037 .halt_reg = 0x04054,
1039 .enable_reg = 0x04054,
1040 .enable_mask = BIT(0),
1054 .halt_reg = 0x05040,
1056 .enable_reg = 0x05040,
1057 .enable_mask = BIT(0),
1071 .halt_reg = 0x06040,
1073 .enable_reg = 0x06040,
1074 .enable_mask = BIT(0),
1088 .halt_reg = 0x07040,
1090 .enable_reg = 0x07040,
1091 .enable_mask = BIT(0),
1105 F(240000000, P_GPLL4, 5, 0, 0),
1110 .cmd_rcgr = 0x28018,
1123 .halt_reg = 0x28038,
1125 .enable_reg = 0x28038,
1126 .enable_mask = BIT(0),
1140 .halt_reg = 0x2e07c,
1142 .enable_reg = 0x2e07c,
1143 .enable_mask = BIT(0),
1157 .cmd_rcgr = 0x29018,
1170 .halt_reg = 0x29038,
1172 .enable_reg = 0x29038,
1173 .enable_mask = BIT(0),
1187 .halt_reg = 0x2e08c,
1189 .enable_reg = 0x2e08c,
1190 .enable_mask = BIT(0),
1204 F(342857143, P_GPLL4, 3.5, 0, 0),
1209 .cmd_rcgr = 0x2a018,
1222 .halt_reg = 0x2a038,
1224 .enable_reg = 0x2a038,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0x2e080,
1241 .enable_reg = 0x2e080,
1242 .enable_mask = BIT(0),
1256 .cmd_rcgr = 0x2b018,
1269 .halt_reg = 0x2b038,
1271 .enable_reg = 0x2b038,
1272 .enable_mask = BIT(0),
1286 .halt_reg = 0x2e090,
1288 .enable_reg = 0x2e090,
1289 .enable_mask = BIT(0),
1303 .cmd_rcgr = 0x28020,
1316 .halt_reg = 0x2803c,
1318 .enable_reg = 0x2803c,
1319 .enable_mask = BIT(0),
1333 .halt_reg = 0x28040,
1335 .enable_reg = 0x28040,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0x2e048,
1352 .enable_reg = 0x2e048,
1353 .enable_mask = BIT(0),
1367 .cmd_rcgr = 0x29020,
1380 .halt_reg = 0x2903c,
1382 .enable_reg = 0x2903c,
1383 .enable_mask = BIT(0),
1397 .halt_reg = 0x29040,
1399 .enable_reg = 0x29040,
1400 .enable_mask = BIT(0),
1414 .halt_reg = 0x2e04c,
1416 .enable_reg = 0x2e04c,
1417 .enable_mask = BIT(0),
1431 .cmd_rcgr = 0x2a020,
1444 .halt_reg = 0x2a03c,
1446 .enable_reg = 0x2a03c,
1447 .enable_mask = BIT(0),
1461 .halt_reg = 0x2a040,
1463 .enable_reg = 0x2a040,
1464 .enable_mask = BIT(0),
1478 .halt_reg = 0x2e050,
1480 .enable_reg = 0x2e050,
1481 .enable_mask = BIT(0),
1495 .cmd_rcgr = 0x2b020,
1508 .halt_reg = 0x2b03c,
1510 .enable_reg = 0x2b03c,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x2b040,
1527 .enable_reg = 0x2b040,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x2e054,
1544 .enable_reg = 0x2e054,
1545 .enable_mask = BIT(0),
1559 .reg = 0x28064,
1573 .reg = 0x29064,
1587 .reg = 0x2a064,
1601 .reg = 0x2b064,
1615 F(24000000, P_XO, 1, 0, 0),
1616 F(100000000, P_GPLL0, 8, 0, 0),
1621 .cmd_rcgr = 0x28028,
1634 .halt_reg = 0x28028,
1636 .enable_reg = 0x28028,
1652 .cmd_rcgr = 0x29028,
1665 .halt_reg = 0x29028,
1667 .enable_reg = 0x29028,
1682 .cmd_rcgr = 0x2a028,
1695 .halt_reg = 0x2a028,
1697 .enable_reg = 0x2a028,
1712 .cmd_rcgr = 0x2b028,
1725 .halt_reg = 0x2b028,
1727 .enable_reg = 0x2b028,
1747 .cmd_rcgr = 0x28004,
1761 .halt_reg = 0x28034,
1763 .enable_reg = 0x28034,
1764 .enable_mask = BIT(0),
1778 .halt_reg = 0x29034,
1780 .enable_reg = 0x29034,
1781 .enable_mask = BIT(0),
1795 .halt_reg = 0x2a034,
1797 .enable_reg = 0x2a034,
1798 .enable_mask = BIT(0),
1812 .halt_reg = 0x2b034,
1814 .enable_reg = 0x2b034,
1815 .enable_mask = BIT(0),
1829 F(24000000, P_XO, 1, 0, 0),
1834 .cmd_rcgr = 0x2c018,
1848 .halt_reg = 0x2c048,
1850 .enable_reg = 0x2c048,
1851 .enable_mask = BIT(0),
1865 F(100000000, P_GPLL0, 8, 0, 0),
1866 F(200000000, P_GPLL0, 4, 0, 0),
1871 .cmd_rcgr = 0x2c004,
1885 .halt_reg = 0x2c044,
1887 .enable_reg = 0x2c044,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0x2e058,
1904 .enable_reg = 0x2e058,
1905 .enable_mask = BIT(0),
1919 .halt_reg = 0x2e084,
1921 .enable_reg = 0x2e084,
1922 .enable_mask = BIT(0),
1936 F(24000000, P_XO, 1, 0, 0),
1942 .cmd_rcgr = 0x2c02c,
1956 .reg = 0x2c040,
1957 .shift = 0,
1971 .halt_reg = 0x2c04c,
1973 .enable_reg = 0x2c04c,
1974 .enable_mask = BIT(0),
1988 .reg = 0x2C074,
2004 .halt_reg = 0x2c054,
2007 .enable_reg = 0x2c054,
2008 .enable_mask = BIT(0),
2022 .halt_reg = 0x2c058,
2024 .enable_reg = 0x2c058,
2025 .enable_mask = BIT(0),
2043 F(96000000, P_GPLL2, 12, 0, 0),
2044 F(177777778, P_GPLL0, 4.5, 0, 0),
2045 F(192000000, P_GPLL2, 6, 0, 0),
2046 F(384000000, P_GPLL2, 3, 0, 0),
2047 F(400000000, P_GPLL0, 2, 0, 0),
2052 .cmd_rcgr = 0x33004,
2066 .halt_reg = 0x3302c,
2068 .enable_reg = 0x3302c,
2069 .enable_mask = BIT(0),
2083 F(150000000, P_GPLL4, 8, 0, 0),
2084 F(300000000, P_GPLL4, 4, 0, 0),
2089 .cmd_rcgr = 0x33018,
2103 .halt_reg = 0x33030,
2105 .enable_reg = 0x33030,
2106 .enable_mask = BIT(0),
2120 F(24000000, P_XO, 1, 0, 0),
2121 F(50000000, P_GPLL0, 16, 0, 0),
2122 F(80000000, P_GPLL0, 10, 0, 0),
2123 F(100000000, P_GPLL0, 8, 0, 0),
2128 .cmd_rcgr = 0x31004,
2142 .halt_reg = 0x16010,
2145 .enable_reg = 0xb004,
2159 .halt_reg = 0x16014,
2162 .enable_reg = 0xb004,
2176 .halt_reg = 0x1702c,
2178 .enable_reg = 0x1702c,
2179 .enable_mask = BIT(0),
2193 .halt_reg = 0x17030,
2195 .enable_reg = 0x17030,
2196 .enable_mask = BIT(0),
2210 .halt_reg = 0x17034,
2212 .enable_reg = 0x17034,
2213 .enable_mask = BIT(0),
2227 .halt_reg = 0x17080,
2229 .enable_reg = 0x17080,
2230 .enable_mask = BIT(0),
2244 .halt_reg = 0x2d064,
2246 .enable_reg = 0x2d064,
2247 .enable_mask = BIT(0),
2261 .halt_reg = 0x2d068,
2263 .enable_reg = 0x2d068,
2264 .enable_mask = BIT(0),
2278 .halt_reg = 0x32010,
2280 .enable_reg = 0x32010,
2281 .enable_mask = BIT(0),
2295 .halt_reg = 0x32014,
2297 .enable_reg = 0x32014,
2298 .enable_mask = BIT(0),
2312 .halt_reg = 0x01004,
2315 .enable_reg = 0x0b004,
2330 .halt_reg = 0x17040,
2332 .enable_reg = 0x17040,
2333 .enable_mask = BIT(0),
2347 .halt_reg = 0x13024,
2350 .enable_reg = 0x0b004,
2365 .halt_reg = 0x1704c,
2367 .enable_reg = 0x1704c,
2368 .enable_mask = BIT(0),
2382 .halt_reg = 0x1705c,
2384 .enable_reg = 0x1705c,
2385 .enable_mask = BIT(0),
2399 .halt_reg = 0x1706c,
2401 .enable_reg = 0x1706c,
2402 .enable_mask = BIT(0),
2416 .halt_reg = 0x3a004,
2418 .enable_reg = 0x3a004,
2419 .enable_mask = BIT(0),
2433 .halt_reg = 0x3a00c,
2435 .enable_reg = 0x3a00c,
2436 .enable_mask = BIT(0),
2450 .halt_reg = 0x28030,
2452 .enable_reg = 0x28030,
2453 .enable_mask = BIT(0),
2467 .halt_reg = 0x29030,
2469 .enable_reg = 0x29030,
2470 .enable_mask = BIT(0),
2484 .halt_reg = 0x2a030,
2486 .enable_reg = 0x2a030,
2487 .enable_mask = BIT(0),
2501 .halt_reg = 0x2b030,
2503 .enable_reg = 0x2b030,
2504 .enable_mask = BIT(0),
2518 .halt_reg = 0x2c05c,
2520 .enable_reg = 0x2c05c,
2521 .enable_mask = BIT(0),
2535 .halt_reg = 0x33034,
2537 .enable_reg = 0x33034,
2538 .enable_mask = BIT(0),
2552 F(24000000, P_XO, 1, 0, 0),
2553 F(133333333, P_GPLL0, 6, 0, 0),
2554 F(200000000, P_GPLL0, 4, 0, 0),
2555 F(342850000, P_GPLL4, 3.5, 0, 0),
2560 .cmd_rcgr = 0x2e004,
2574 .halt_reg = 0x25080,
2577 .enable_reg = 0x25080,
2578 .enable_mask = BIT(0),
2592 .halt_reg = 0x17028,
2594 .enable_reg = 0x17028,
2595 .enable_mask = BIT(0),
2609 .halt_reg = 0x1707c,
2611 .enable_reg = 0x1707c,
2612 .enable_mask = BIT(0),
2626 .halt_reg = 0x2d060,
2628 .enable_reg = 0x2d060,
2629 .enable_mask = BIT(0),
2643 F(24000000, P_XO, 1, 0, 0),
2644 F(133333333, P_GPLL0, 6, 0, 0),
2649 .cmd_rcgr = 0x25030,
2662 .halt_reg = 0x25014,
2664 .enable_reg = 0x25014,
2665 .enable_mask = BIT(0),
2679 .halt_reg = 0x25018,
2681 .enable_reg = 0x25018,
2682 .enable_mask = BIT(0),
2696 .halt_reg = 0x25058,
2698 .enable_reg = 0x25058,
2699 .enable_mask = BIT(0),
2713 .halt_reg = 0x2505c,
2715 .enable_reg = 0x2505c,
2716 .enable_mask = BIT(0),
2730 .halt_reg = 0x2e030,
2732 .enable_reg = 0x2e030,
2733 .enable_mask = BIT(0),
2747 F(24000000, P_XO, 1, 0, 0),
2748 F(133333333, P_GPLL0, 6, 0, 0),
2749 F(266666667, P_GPLL0, 3, 0, 0),
2754 .cmd_rcgr = 0x25078,
2767 .halt_reg = 0x2e0a8,
2769 .enable_reg = 0x2e0a8,
2770 .enable_mask = BIT(0),
2784 F(240000000, P_GPLL4, 5, 0, 0),
2789 .cmd_rcgr = 0x2d004,
2802 .halt_reg = 0x2501c,
2804 .enable_reg = 0x2501c,
2805 .enable_mask = BIT(0),
2819 .halt_reg = 0x2503c,
2821 .enable_reg = 0x2503c,
2822 .enable_mask = BIT(0),
2836 .halt_reg = 0x17014,
2838 .enable_reg = 0x17014,
2839 .enable_mask = BIT(0),
2853 .halt_reg = 0x2d038,
2855 .enable_reg = 0x2d038,
2856 .enable_mask = BIT(0),
2870 .halt_reg = 0x2e038,
2872 .enable_reg = 0x2e038,
2873 .enable_mask = BIT(0),
2887 .halt_reg = 0x31024,
2889 .enable_reg = 0x31024,
2890 .enable_mask = BIT(0),
2918 .halt_reg = 0x30004,
2920 .enable_reg = 0x30004,
2921 .enable_mask = BIT(0),
2935 .halt_reg = 0x2d06c,
2937 .enable_reg = 0x2d06c,
2938 .enable_mask = BIT(0),
2952 F(24000000, P_XO, 1, 0, 0),
2953 F(200000000, P_GPLL0, 4, 0, 0),
2958 .cmd_rcgr = 0x2d00c,
2971 .halt_reg = 0x2d03c,
2973 .enable_reg = 0x2d03c,
2974 .enable_mask = BIT(0),
2988 .halt_reg = 0x2e034,
2990 .enable_reg = 0x2e034,
2991 .enable_mask = BIT(0),
3005 F(300000000, P_GPLL4, 4, 0, 0),
3010 .cmd_rcgr = 0x2d014,
3023 .halt_reg = 0x2d040,
3025 .enable_reg = 0x2d040,
3026 .enable_mask = BIT(0),
3040 F(600000000, P_GPLL4, 2, 0, 0),
3045 .cmd_rcgr = 0x2d01c,
3072 .halt_reg = 0x25020,
3074 .enable_reg = 0x25020,
3075 .enable_mask = BIT(0),
3089 .halt_reg = 0x25040,
3091 .enable_reg = 0x25040,
3092 .enable_mask = BIT(0),
3106 .halt_reg = 0x2d044,
3108 .enable_reg = 0x2d044,
3109 .enable_mask = BIT(0),
3123 F(24000000, P_XO, 1, 0, 0),
3128 .cmd_rcgr = 0x17090,
3142 .cmd_rcgr = 0x17088,
3156 .halt_reg = 0x2d078,
3158 .enable_reg = 0x2d078,
3159 .enable_mask = BIT(0),
3186 .halt_reg = 0x2d04c,
3188 .enable_reg = 0x2d04c,
3189 .enable_mask = BIT(0),
3216 .halt_reg = 0x17018,
3218 .enable_reg = 0x17018,
3219 .enable_mask = BIT(0),
3233 .halt_reg = 0x2d050,
3235 .enable_reg = 0x2d050,
3236 .enable_mask = BIT(0),
3263 .halt_reg = 0x2d054,
3265 .enable_reg = 0x2d054,
3266 .enable_mask = BIT(0),
3280 .halt_reg = 0x25024,
3282 .enable_reg = 0x25024,
3283 .enable_mask = BIT(0),
3297 .halt_reg = 0x25068,
3299 .enable_reg = 0x25068,
3300 .enable_mask = BIT(0),
3314 .halt_reg = 0x25038,
3316 .enable_reg = 0x25038,
3317 .enable_mask = BIT(0),
3331 .halt_reg = 0x25044,
3333 .enable_reg = 0x25044,
3334 .enable_mask = BIT(0),
3348 .halt_reg = 0x2d058,
3350 .enable_reg = 0x2d058,
3351 .enable_mask = BIT(0),
3365 .halt_reg = 0x2d05c,
3367 .enable_reg = 0x2d05c,
3368 .enable_mask = BIT(0),
3395 .halt_reg = 0x2d048,
3397 .enable_reg = 0x2d048,
3398 .enable_mask = BIT(0),
3412 F(24000000, P_XO, 1, 0, 0),
3413 F(100000000, P_GPLL0, 8, 0, 0),
3414 F(200000000, P_GPLL0, 4, 0, 0),
3415 F(320000000, P_GPLL0, 2.5, 0, 0),
3416 F(400000000, P_GPLL0, 2, 0, 0),
3421 .cmd_rcgr = 0x32004,
3434 .halt_reg = 0x3200c,
3436 .enable_reg = 0x3200c,
3437 .enable_mask = BIT(0),
3451 F(533333333, P_GPLL0, 1.5, 0, 0),
3456 .cmd_rcgr = 0x25004,
3469 .halt_reg = 0x2500c,
3471 .enable_reg = 0x2500c,
3472 .enable_mask = BIT(0),
3486 .halt_reg = 0x12050,
3489 .enable_reg = 0xb00c,
3504 .halt_reg = 0x19010,
3506 .enable_reg = 0x19010,
3507 .enable_mask = BIT(0),
3521 F(342857143, P_GPLL4, 3.5, 0, 0),
3526 { P_XO, 0 },
3533 .cmd_rcgr = 0x25028,
3546 F(533333333, P_GPLL0, 1.5, 0, 0),
3551 .cmd_rcgr = 0x17004,
3564 .halt_reg = 0x17024,
3566 .enable_reg = 0x17024,
3567 .enable_mask = BIT(0),
3581 .halt_reg = 0x17084,
3583 .enable_reg = 0x17084,
3584 .enable_mask = BIT(0),
3598 .halt_reg = 0x12040,
3600 .enable_reg = 0xb00c,
3615 .halt_reg = 0x19014,
3617 .enable_reg = 0x19014,
3618 .enable_mask = BIT(0),
3632 F(133333333, P_GPLL0, 6, 0, 0),
3637 .cmd_rcgr = 0x2700c,
3650 .cmd_rcgr = 0x27004,
3663 F(24000000, P_XO, 1, 0, 0),
3664 F(100000000, P_GPLL0, 8, 0, 0),
3669 .cmd_rcgr = 0x1c004,
3682 .halt_reg = 0x1c00c,
3684 .enable_reg = 0x1c00c,
3685 .enable_mask = BIT(0),
3699 F(24000000, P_XO, 1, 0, 0),
3700 F(200000000, P_GPLL0, 4, 0, 0),
3705 .cmd_rcgr = 0x8004,
3718 .cmd_rcgr = 0x9004,
3731 .cmd_rcgr = 0xa004,
3744 .halt_reg = 0x34004,
3746 .enable_reg = 0x34004,
3759 .halt_reg = 0x17074,
3761 .enable_reg = 0x17074,
3762 .enable_mask = BIT(0),
3776 .halt_reg = 0x34018,
3778 .enable_reg = 0x34018,
3779 .enable_mask = BIT(0),
3793 .halt_reg = 0x17048,
3795 .enable_reg = 0x17048,
3796 .enable_mask = BIT(0),
3810 .halt_reg = 0x17058,
3812 .enable_reg = 0x17058,
3813 .enable_mask = BIT(0),
3827 .halt_reg = 0x17068,
3829 .enable_reg = 0x17068,
3830 .enable_mask = BIT(0),
3844 .halt_reg = 0x3a008,
3846 .enable_reg = 0x3a008,
3847 .enable_mask = BIT(0),
3875 .halt_reg = 0x1701c,
3877 .enable_reg = 0x1701c,
3878 .enable_mask = BIT(0),
3892 .halt_reg = 0x17020,
3894 .enable_reg = 0x17020,
3895 .enable_mask = BIT(0),
3909 .halt_reg = 0x3401c,
3911 .enable_reg = 0x3401c,
3912 .enable_mask = BIT(0),
4149 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4150 [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
4151 [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
4152 [GCC_ANOC_BCR] = { 0x2e074, 0 },
4153 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
4154 [GCC_APSS_TCU_BCR] = { 0x12014, 0 },
4155 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4156 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4157 [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
4158 [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
4159 [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
4160 [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
4161 [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
4162 [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
4163 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4164 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4165 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4166 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4167 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4168 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
4169 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
4170 [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
4171 [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
4172 [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
4173 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4174 [GCC_DCC_BCR] = { 0x35000, 0 },
4175 [GCC_DDRSS_BCR] = { 0x11000, 0 },
4176 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4177 [GCC_LPASS_BCR] = { 0x27000, 0 },
4178 [GCC_MDIO_BCR] = { 0x1703c, 0 },
4179 [GCC_MPM_BCR] = { 0x37000, 0 },
4180 [GCC_MSG_RAM_BCR] = { 0x26000, 0 },
4181 [GCC_NSS_BCR] = { 0x17000, 0 },
4182 [GCC_NSS_TBU_BCR] = { 0x12044, 0 },
4183 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
4184 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
4185 [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 },
4186 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 },
4187 [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
4188 [GCC_NSSCC_ARES] = { 0x17038, 8 },
4189 [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
4190 [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
4191 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
4192 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
4193 [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
4194 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
4195 [GCC_NSS_CFG_ARES] = { 0x17038, 1 },
4196 [GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
4197 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
4198 [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
4199 [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
4200 [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
4201 [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
4202 [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
4203 [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
4204 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
4205 [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
4206 [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
4207 [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
4208 [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
4209 [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
4210 [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
4211 [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
4212 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
4213 [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
4214 [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
4215 [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
4216 [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
4217 [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
4218 [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
4219 [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
4220 [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
4221 [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
4222 [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
4223 [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
4224 [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
4225 [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
4226 [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
4227 [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
4228 [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
4229 [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
4230 [GCC_PCIE0_BCR] = { 0x28000, 0 },
4231 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4232 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4233 [GCC_PCIE1_BCR] = { 0x29000, 0 },
4234 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4235 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4236 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4237 [GCC_PCIE2_BCR] = { 0x2a000, 0 },
4238 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4239 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4240 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4241 [GCC_PCIE3_BCR] = { 0x2b000, 0 },
4242 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4243 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4244 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4245 [GCC_PCNOC_BCR] = { 0x31000, 0 },
4246 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4247 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4248 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4249 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4250 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4251 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4252 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4253 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4254 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4255 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4256 [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4257 [GCC_PRNG_BCR] = { 0x13020, 0 },
4258 [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4259 [GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4260 [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4261 [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4262 [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4263 [GCC_QDSS_BCR] = { 0x2d000, 0 },
4264 [GCC_QPIC_BCR] = { 0x32000, 0 },
4265 [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4266 [GCC_QPIC_ARES] = { 0x3201c, 0 },
4267 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4268 [GCC_RBCPR_BCR] = { 0x39000, 0 },
4269 [GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4270 [GCC_SDCC_BCR] = { 0x33000, 0 },
4271 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4272 [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4273 [GCC_SNOC_BCR] = { 0x2e000, 0 },
4274 [GCC_SPDM_BCR] = { 0x36000, 0 },
4275 [GCC_TCSR_BCR] = { 0x3d000, 0 },
4276 [GCC_TLMM_BCR] = { 0x3e000, 0 },
4277 [GCC_TME_BCR] = { 0x10000, 0 },
4278 [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4279 [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4280 [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4281 [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4282 [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4283 [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4284 [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4285 [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4286 [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4287 [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4288 [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4289 [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4290 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4291 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4292 [GCC_USB_BCR] = { 0x2c000, 0 },
4293 [GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4294 [GCC_WCSSAON_RESET] = { 0x25074, 0 },
4295 [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4296 [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4297 [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4298 [GCC_WCSS_BCR] = { 0x18004, 0 },
4299 [GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4300 [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4301 [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4302 [GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4303 [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4316 .max_register = 0x7fffc,