Lines Matching refs:name
58 .name = "gpll0_main",
61 .name = "xo",
73 .name = "gpll0_out_main_div2",
86 .name = "gpll0",
101 .name = "gpll2_main",
104 .name = "xo",
118 .name = "gpll2",
133 .name = "gpll4_main",
136 .name = "xo",
150 .name = "gpll4",
166 .name = "gpll6_main",
169 .name = "xo",
183 .name = "gpll6",
195 .name = "gpll6_out_main_div2",
211 .name = "ubi32_pll_main",
214 .name = "xo",
227 .name = "ubi32_pll",
243 .name = "nss_crypto_pll_main",
246 .name = "xo",
259 .name = "nss_crypto_pll",
275 { .fw_name = "xo", .name = "xo" },
292 .name = "pcnoc_bfdcd_clk_src",
304 .name = "pcnoc_clk_src",
319 .name = "gcc_sleep_clk_src",
322 .name = "sleep_clk",
344 .name = "blsp1_qup1_i2c_apps_clk_src",
370 .name = "blsp1_qup1_spi_apps_clk_src",
383 .name = "blsp1_qup2_i2c_apps_clk_src",
397 .name = "blsp1_qup2_spi_apps_clk_src",
410 .name = "blsp1_qup3_i2c_apps_clk_src",
424 .name = "blsp1_qup3_spi_apps_clk_src",
437 .name = "blsp1_qup4_i2c_apps_clk_src",
451 .name = "blsp1_qup4_spi_apps_clk_src",
464 .name = "blsp1_qup5_i2c_apps_clk_src",
478 .name = "blsp1_qup5_spi_apps_clk_src",
491 .name = "blsp1_qup6_i2c_apps_clk_src",
505 .name = "blsp1_qup6_spi_apps_clk_src",
539 .name = "blsp1_uart1_apps_clk_src",
553 .name = "blsp1_uart2_apps_clk_src",
567 .name = "blsp1_uart3_apps_clk_src",
581 .name = "blsp1_uart4_apps_clk_src",
595 .name = "blsp1_uart5_apps_clk_src",
609 .name = "blsp1_uart6_apps_clk_src",
638 .name = "pcie0_axi_clk_src",
651 { .fw_name = "xo", .name = "xo" },
653 { .fw_name = "sleep_clk", .name = "sleep_clk" },
669 .name = "pcie0_aux_clk_src",
677 { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
678 { .fw_name = "xo", .name = "xo" },
693 .name = "pcie0_pipe_clk_src",
708 .name = "pcie1_axi_clk_src",
722 .name = "pcie1_aux_clk_src",
730 { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
731 { .fw_name = "xo", .name = "xo" },
746 .name = "pcie1_pipe_clk_src",
768 { .fw_name = "xo", .name = "xo" },
788 .name = "sdcc1_apps_clk_src",
803 { .fw_name = "xo", .name = "xo" },
823 .name = "sdcc1_ice_core_clk_src",
837 .name = "sdcc2_apps_clk_src",
852 { .fw_name = "xo", .name = "xo" },
870 .name = "usb0_master_clk_src",
889 .name = "usb0_aux_clk_src",
904 { .fw_name = "xo", .name = "xo" },
924 .name = "usb0_mock_utmi_clk_src",
932 { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
933 { .fw_name = "xo", .name = "xo" },
948 .name = "usb0_pipe_clk_src",
964 .name = "usb1_master_clk_src",
978 .name = "usb1_aux_clk_src",
992 .name = "usb1_mock_utmi_clk_src",
1000 { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
1001 { .fw_name = "xo", .name = "xo" },
1016 .name = "usb1_pipe_clk_src",
1031 .name = "gcc_xo_clk_src",
1034 .name = "xo",
1047 .name = "gcc_xo_div4_clk_src",
1068 { .fw_name = "xo", .name = "xo" },
1087 .name = "system_noc_bfdcd_clk_src",
1099 .name = "system_noc_clk_src",
1120 .name = "nss_ce_clk_src",
1134 { .fw_name = "xo", .name = "xo" },
1135 { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
1153 .name = "nss_noc_bfdcd_clk_src",
1164 .name = "nss_noc_clk_src",
1180 { .fw_name = "xo", .name = "xo" },
1198 .name = "nss_crypto_clk_src",
1215 { .fw_name = "xo", .name = "xo" },
1238 .name = "nss_ubi0_clk_src",
1252 .name = "nss_ubi0_div_clk_src",
1268 .name = "nss_ubi1_clk_src",
1282 .name = "nss_ubi1_div_clk_src",
1299 { .fw_name = "xo", .name = "xo" },
1314 .name = "ubi_mpt_clk_src",
1328 { .fw_name = "xo", .name = "xo" },
1345 .name = "nss_imem_clk_src",
1359 { .fw_name = "xo", .name = "xo" },
1360 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1382 .name = "nss_ppe_clk_src",
1393 .name = "nss_ppe_cdiv_clk_src",
1410 { .fw_name = "xo", .name = "xo" },
1411 { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1412 { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1414 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1431 .name = "nss_port1_rx_clk_src",
1444 .name = "nss_port1_rx_div_clk_src",
1462 { .fw_name = "xo", .name = "xo" },
1463 { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1464 { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1466 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1483 .name = "nss_port1_tx_clk_src",
1496 .name = "nss_port1_tx_div_clk_src",
1512 .name = "nss_port2_rx_clk_src",
1525 .name = "nss_port2_rx_div_clk_src",
1541 .name = "nss_port2_tx_clk_src",
1554 .name = "nss_port2_tx_div_clk_src",
1570 .name = "nss_port3_rx_clk_src",
1583 .name = "nss_port3_rx_div_clk_src",
1599 .name = "nss_port3_tx_clk_src",
1612 .name = "nss_port3_tx_div_clk_src",
1628 .name = "nss_port4_rx_clk_src",
1641 .name = "nss_port4_rx_div_clk_src",
1657 .name = "nss_port4_tx_clk_src",
1670 .name = "nss_port4_tx_div_clk_src",
1693 { .fw_name = "xo", .name = "xo" },
1694 { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1695 { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1696 { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1697 { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1699 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1719 .name = "nss_port5_rx_clk_src",
1732 .name = "nss_port5_rx_div_clk_src",
1755 { .fw_name = "xo", .name = "xo" },
1756 { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
1757 { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
1758 { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
1759 { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
1761 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1781 .name = "nss_port5_tx_clk_src",
1794 .name = "nss_port5_tx_div_clk_src",
1817 { .fw_name = "xo", .name = "xo" },
1818 { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1819 { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1821 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1838 .name = "nss_port6_rx_clk_src",
1851 .name = "nss_port6_rx_div_clk_src",
1874 { .fw_name = "xo", .name = "xo" },
1875 { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
1876 { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
1878 { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
1895 .name = "nss_port6_tx_clk_src",
1908 .name = "nss_port6_tx_div_clk_src",
1932 .name = "crypto_clk_src",
1945 { .fw_name = "xo", .name = "xo" },
1949 { .fw_name = "sleep_clk", .name = "sleep_clk" },
1967 .name = "gp1_clk_src",
1981 .name = "gp2_clk_src",
1995 .name = "gp3_clk_src",
2008 .name = "gcc_blsp1_ahb_clk",
2024 .name = "gcc_blsp1_qup1_i2c_apps_clk",
2040 .name = "gcc_blsp1_qup1_spi_apps_clk",
2056 .name = "gcc_blsp1_qup2_i2c_apps_clk",
2072 .name = "gcc_blsp1_qup2_spi_apps_clk",
2088 .name = "gcc_blsp1_qup3_i2c_apps_clk",
2104 .name = "gcc_blsp1_qup3_spi_apps_clk",
2120 .name = "gcc_blsp1_qup4_i2c_apps_clk",
2136 .name = "gcc_blsp1_qup4_spi_apps_clk",
2152 .name = "gcc_blsp1_qup5_i2c_apps_clk",
2168 .name = "gcc_blsp1_qup5_spi_apps_clk",
2184 .name = "gcc_blsp1_qup6_i2c_apps_clk",
2200 .name = "gcc_blsp1_qup6_spi_apps_clk",
2216 .name = "gcc_blsp1_uart1_apps_clk",
2232 .name = "gcc_blsp1_uart2_apps_clk",
2248 .name = "gcc_blsp1_uart3_apps_clk",
2264 .name = "gcc_blsp1_uart4_apps_clk",
2280 .name = "gcc_blsp1_uart5_apps_clk",
2296 .name = "gcc_blsp1_uart6_apps_clk",
2313 .name = "gcc_prng_ahb_clk",
2329 .name = "gcc_qpic_ahb_clk",
2345 .name = "gcc_qpic_clk",
2361 .name = "gcc_pcie0_ahb_clk",
2377 .name = "gcc_pcie0_aux_clk",
2393 .name = "gcc_pcie0_axi_m_clk",
2409 .name = "gcc_pcie0_axi_s_clk",
2426 .name = "gcc_pcie0_pipe_clk",
2442 .name = "gcc_sys_noc_pcie0_axi_clk",
2458 .name = "gcc_pcie1_ahb_clk",
2474 .name = "gcc_pcie1_aux_clk",
2490 .name = "gcc_pcie1_axi_m_clk",
2506 .name = "gcc_pcie1_axi_s_clk",
2523 .name = "gcc_pcie1_pipe_clk",
2539 .name = "gcc_sys_noc_pcie1_axi_clk",
2555 .name = "gcc_usb0_aux_clk",
2571 .name = "gcc_sys_noc_usb0_axi_clk",
2587 .name = "gcc_usb0_master_clk",
2603 .name = "gcc_usb0_mock_utmi_clk",
2619 .name = "gcc_usb0_phy_cfg_ahb_clk",
2636 .name = "gcc_usb0_pipe_clk",
2652 .name = "gcc_usb0_sleep_clk",
2668 .name = "gcc_usb1_aux_clk",
2684 .name = "gcc_sys_noc_usb1_axi_clk",
2700 .name = "gcc_usb1_master_clk",
2716 .name = "gcc_usb1_mock_utmi_clk",
2732 .name = "gcc_usb1_phy_cfg_ahb_clk",
2749 .name = "gcc_usb1_pipe_clk",
2765 .name = "gcc_usb1_sleep_clk",
2781 .name = "gcc_sdcc1_ahb_clk",
2797 .name = "gcc_sdcc1_apps_clk",
2813 .name = "gcc_sdcc1_ice_core_clk",
2829 .name = "gcc_sdcc2_ahb_clk",
2845 .name = "gcc_sdcc2_apps_clk",
2861 .name = "gcc_mem_noc_nss_axi_clk",
2877 .name = "gcc_nss_ce_apb_clk",
2893 .name = "gcc_nss_ce_axi_clk",
2909 .name = "gcc_nss_cfg_clk",
2925 .name = "gcc_nss_crypto_clk",
2941 .name = "gcc_nss_csr_clk",
2957 .name = "gcc_nss_edma_cfg_clk",
2973 .name = "gcc_nss_edma_clk",
2989 .name = "gcc_nss_imem_clk",
3005 .name = "gcc_nss_noc_clk",
3021 .name = "gcc_nss_ppe_btq_clk",
3037 .name = "gcc_nss_ppe_cfg_clk",
3053 .name = "gcc_nss_ppe_clk",
3069 .name = "gcc_nss_ppe_ipe_clk",
3085 .name = "gcc_nss_ptp_ref_clk",
3102 .name = "gcc_crypto_ppe_clk",
3118 .name = "gcc_nssnoc_ce_apb_clk",
3134 .name = "gcc_nssnoc_ce_axi_clk",
3150 .name = "gcc_nssnoc_crypto_clk",
3166 .name = "gcc_nssnoc_ppe_cfg_clk",
3182 .name = "gcc_nssnoc_ppe_clk",
3198 .name = "gcc_nssnoc_qosgen_ref_clk",
3214 .name = "gcc_nssnoc_snoc_clk",
3230 .name = "gcc_nssnoc_timeout_ref_clk",
3246 .name = "gcc_nssnoc_ubi0_ahb_clk",
3262 .name = "gcc_nssnoc_ubi1_ahb_clk",
3279 .name = "gcc_ubi0_ahb_clk",
3296 .name = "gcc_ubi0_axi_clk",
3313 .name = "gcc_ubi0_nc_axi_clk",
3330 .name = "gcc_ubi0_core_clk",
3347 .name = "gcc_ubi0_mpt_clk",
3364 .name = "gcc_ubi1_ahb_clk",
3381 .name = "gcc_ubi1_axi_clk",
3398 .name = "gcc_ubi1_nc_axi_clk",
3415 .name = "gcc_ubi1_core_clk",
3432 .name = "gcc_ubi1_mpt_clk",
3448 .name = "gcc_cmn_12gpll_ahb_clk",
3464 .name = "gcc_cmn_12gpll_sys_clk",
3480 .name = "gcc_mdio_ahb_clk",
3496 .name = "gcc_uniphy0_ahb_clk",
3512 .name = "gcc_uniphy0_sys_clk",
3528 .name = "gcc_uniphy1_ahb_clk",
3544 .name = "gcc_uniphy1_sys_clk",
3560 .name = "gcc_uniphy2_ahb_clk",
3576 .name = "gcc_uniphy2_sys_clk",
3592 .name = "gcc_nss_port1_rx_clk",
3608 .name = "gcc_nss_port1_tx_clk",
3624 .name = "gcc_nss_port2_rx_clk",
3640 .name = "gcc_nss_port2_tx_clk",
3656 .name = "gcc_nss_port3_rx_clk",
3672 .name = "gcc_nss_port3_tx_clk",
3688 .name = "gcc_nss_port4_rx_clk",
3704 .name = "gcc_nss_port4_tx_clk",
3720 .name = "gcc_nss_port5_rx_clk",
3736 .name = "gcc_nss_port5_tx_clk",
3752 .name = "gcc_nss_port6_rx_clk",
3768 .name = "gcc_nss_port6_tx_clk",
3784 .name = "gcc_port1_mac_clk",
3800 .name = "gcc_port2_mac_clk",
3816 .name = "gcc_port3_mac_clk",
3832 .name = "gcc_port4_mac_clk",
3848 .name = "gcc_port5_mac_clk",
3864 .name = "gcc_port6_mac_clk",
3880 .name = "gcc_uniphy0_port1_rx_clk",
3896 .name = "gcc_uniphy0_port1_tx_clk",
3912 .name = "gcc_uniphy0_port2_rx_clk",
3928 .name = "gcc_uniphy0_port2_tx_clk",
3944 .name = "gcc_uniphy0_port3_rx_clk",
3960 .name = "gcc_uniphy0_port3_tx_clk",
3976 .name = "gcc_uniphy0_port4_rx_clk",
3992 .name = "gcc_uniphy0_port4_tx_clk",
4008 .name = "gcc_uniphy0_port5_rx_clk",
4024 .name = "gcc_uniphy0_port5_tx_clk",
4040 .name = "gcc_uniphy1_port5_rx_clk",
4056 .name = "gcc_uniphy1_port5_tx_clk",
4072 .name = "gcc_uniphy2_port6_rx_clk",
4088 .name = "gcc_uniphy2_port6_tx_clk",
4105 .name = "gcc_crypto_ahb_clk",
4122 .name = "gcc_crypto_axi_clk",
4139 .name = "gcc_crypto_clk",
4155 .name = "gcc_gp1_clk",
4171 .name = "gcc_gp2_clk",
4187 .name = "gcc_gp3_clk",
4209 .name = "pcie0_rchng_clk_src",
4223 .name = "gcc_pcie0_rchng_clk",
4241 .name = "gcc_pcie0_axi_s_bridge_clk",
4255 .name = "usb0_gdsc",
4263 .name = "usb1_gdsc",
4737 .name = "qcom,gcc-ipq8074",