Lines Matching +full:0 +full:x37000
50 .offset = 0x21000,
53 .enable_reg = 0x0b000,
54 .enable_mask = BIT(0),
79 .offset = 0x21000,
98 { P_XO, 0 },
104 .offset = 0x25000,
108 .enable_reg = 0x0b000,
122 .offset = 0x25000,
136 .offset = 0x37000,
139 .enable_reg = 0x0b000,
153 .offset = 0x37000,
166 .offset = 0x24000,
169 .enable_reg = 0x0b000,
183 .offset = 0x24000,
196 F(24000000, P_XO, 1, 0, 0),
197 F(50000000, P_GPLL0, 16, 0, 0),
198 F(100000000, P_GPLL0, 8, 0, 0),
203 .cmd_rcgr = 0x27000,
216 .offset = 0x4a000,
219 .enable_reg = 0x0b000,
233 .offset = 0x4a000,
246 .offset = 0x22000,
249 .enable_reg = 0x0b000,
263 .offset = 0x22000,
276 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
277 F(320000000, P_GPLL0, 2.5, 0, 0),
278 F(600000000, P_GPLL4, 2, 0, 0),
291 { P_XO, 0 },
299 .cmd_rcgr = 0x29064,
324 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
325 F(240000000, P_GPLL4, 5, 0, 0),
330 .cmd_rcgr = 0x2900c,
356 F(24000000, P_XO, 1, 0, 0),
357 F(300000000, P_BIAS_PLL, 1, 0, 0),
371 { P_XO, 0 },
380 .cmd_rcgr = 0x68080,
393 .halt_reg = 0x30018,
395 .enable_reg = 0x30018,
410 F(24000000, P_XO, 1, 0, 0),
411 F(200000000, P_GPLL0, 4, 0, 0),
421 { P_XO, 0 },
426 .cmd_rcgr = 0x68098,
439 .halt_reg = 0x30000,
441 .enable_reg = 0x30000,
455 F(24000000, P_XO, 1, 0, 0),
456 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
457 F(100000000, P_GPLL0, 8, 0, 0),
458 F(133333333, P_GPLL0, 6, 0, 0),
459 F(160000000, P_GPLL0, 5, 0, 0),
460 F(200000000, P_GPLL0, 4, 0, 0),
461 F(266666667, P_GPLL0, 3, 0, 0),
474 { P_XO, 0 },
481 .cmd_rcgr = 0x76054,
494 F(24000000, P_XO, 1, 0, 0),
495 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
496 F(50000000, P_GPLL0, 16, 0, 0),
497 F(100000000, P_GPLL0, 8, 0, 0),
502 .cmd_rcgr = 0x46000,
515 F(24000000, P_XO, 1, 0, 0),
516 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
517 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
518 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
519 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
520 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
521 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
522 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
539 { P_XO, 0 },
549 .cmd_rcgr = 0x68060,
562 F(24000000, P_XO, 1, 0, 0),
563 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
564 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
565 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
566 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
567 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
568 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
569 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
586 { P_XO, 0 },
596 .cmd_rcgr = 0x68068,
609 F(24000000, P_XO, 1, 0, 0),
610 F(200000000, P_GPLL0, 4, 0, 0),
611 F(240000000, P_GPLL4, 5, 0, 0),
616 F(24000000, P_XO, 1, 0, 0),
617 F(100000000, P_GPLL0, 8, 0, 0),
628 { P_XO, 0 },
634 .cmd_rcgr = 0x75054,
647 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
648 F(100000000, P_GPLL0, 8, 0, 0),
649 F(133330000, P_GPLL0, 6, 0, 0),
650 F(200000000, P_GPLL0, 4, 0, 0),
661 { P_XO, 0 },
667 .cmd_rcgr = 0x3e00c,
681 .reg = 0x46018,
709 F(24000000, P_XO, 1, 0, 0),
710 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
711 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
724 { P_XO, 0 },
732 .cmd_rcgr = 0x68020,
745 F(24000000, P_XO, 1, 0, 0),
746 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
747 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
760 { P_XO, 0 },
768 .cmd_rcgr = 0x68028,
781 .cmd_rcgr = 0x68030,
794 .cmd_rcgr = 0x68038,
807 .cmd_rcgr = 0x68040,
820 .cmd_rcgr = 0x68048,
833 .cmd_rcgr = 0x68050,
846 .cmd_rcgr = 0x68058,
859 .reg = 0x68440,
860 .shift = 0,
875 .reg = 0x68444,
876 .shift = 0,
891 F(24000000, P_XO, 1, 0, 0),
892 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
893 F(200000000, P_GPLL0, 4, 0, 0),
894 F(308570000, P_GPLL6, 3.5, 0, 0),
895 F(400000000, P_GPLL0, 2, 0, 0),
896 F(533000000, P_GPLL0, 1.5, 0, 0),
910 { P_XO, 0 },
918 .cmd_rcgr = 0x38048,
931 F(24000000, P_XO, 1, 0, 0),
932 F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
943 { P_XO, 0 },
949 .cmd_rcgr = 0x68144,
963 .reg = 0x68400,
964 .shift = 0,
979 .reg = 0x68404,
980 .shift = 0,
995 .reg = 0x68410,
996 .shift = 0,
1011 .reg = 0x68414,
1012 .shift = 0,
1027 .reg = 0x68420,
1028 .shift = 0,
1043 .reg = 0x68424,
1044 .shift = 0,
1059 .reg = 0x68430,
1060 .shift = 0,
1075 .reg = 0x68434,
1076 .shift = 0,
1091 F(24000000, P_XO, 1, 0, 0),
1092 F(149760000, P_UBI32_PLL, 10, 0, 0),
1093 F(187200000, P_UBI32_PLL, 8, 0, 0),
1094 F(249600000, P_UBI32_PLL, 6, 0, 0),
1095 F(374400000, P_UBI32_PLL, 4, 0, 0),
1096 F(748800000, P_UBI32_PLL, 2, 0, 0),
1097 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1112 { P_XO, 0 },
1121 .cmd_rcgr = 0x68104,
1135 F(24000000, P_XO, 1, 0, 0),
1136 F(100000000, P_GPLL0, 8, 0, 0),
1141 .cmd_rcgr = 0x1c008,
1154 F(24000000, P_XO, 1, 0, 0),
1155 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1156 F(50000000, P_GPLL0, 16, 0, 0),
1161 .cmd_rcgr = 0x0200c,
1175 F(4800000, P_XO, 5, 0, 0),
1179 F(24000000, P_XO, 1, 0, 0),
1181 F(50000000, P_GPLL0, 16, 0, 0),
1186 .cmd_rcgr = 0x02024,
1200 .cmd_rcgr = 0x03000,
1213 .cmd_rcgr = 0x03014,
1227 .cmd_rcgr = 0x04000,
1240 .cmd_rcgr = 0x04014,
1254 .cmd_rcgr = 0x05000,
1267 .cmd_rcgr = 0x05014,
1281 .cmd_rcgr = 0x06000,
1294 .cmd_rcgr = 0x06014,
1308 .cmd_rcgr = 0x07000,
1321 .cmd_rcgr = 0x07014,
1339 F(24000000, P_XO, 1, 0, 0),
1355 .cmd_rcgr = 0x02044,
1369 .cmd_rcgr = 0x03034,
1383 .cmd_rcgr = 0x04034,
1397 .cmd_rcgr = 0x05034,
1411 .cmd_rcgr = 0x06034,
1425 .cmd_rcgr = 0x07034,
1439 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1440 F(80000000, P_GPLL0, 10, 0, 0),
1441 F(100000000, P_GPLL0, 8, 0, 0),
1442 F(160000000, P_GPLL0, 5, 0, 0),
1447 .cmd_rcgr = 0x16004,
1460 F(24000000, P_XO, 1, 0, 0),
1461 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1462 F(100000000, P_GPLL0, 8, 0, 0),
1463 F(200000000, P_GPLL0, 4, 0, 0),
1464 F(266666666, P_GPLL0, 3, 0, 0),
1477 { P_XO, 0 },
1485 .cmd_rcgr = 0x08004,
1499 .cmd_rcgr = 0x09004,
1513 .cmd_rcgr = 0x0a004,
1540 .reg = 0x68118,
1541 .shift = 0,
1556 F(24000000, P_XO, 1, 0, 0),
1567 { P_XO, 0 },
1573 .cmd_rcgr = 0x75024,
1592 { P_PCIE20_PHY0_PIPE, 0 },
1597 .reg = 0x7501c,
1617 F(96000000, P_GPLL2, 12, 0, 0),
1618 F(177777778, P_GPLL0, 4.5, 0, 0),
1619 F(192000000, P_GPLL2, 6, 0, 0),
1620 F(384000000, P_GPLL2, 3, 0, 0),
1633 { P_XO, 0 },
1640 .cmd_rcgr = 0x42004,
1654 F(24000000, P_XO, 1, 0, 0),
1659 .cmd_rcgr = 0x3e05c,
1673 F(24000000, P_XO, 1, 0, 0),
1687 { P_XO, 0 },
1694 .cmd_rcgr = 0x3e020,
1713 { P_USB3PHY_0_PIPE, 0 },
1718 .reg = 0x3e048,
1734 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1735 F(160000000, P_GPLL0, 5, 0, 0),
1736 F(216000000, P_GPLL6, 5, 0, 0),
1737 F(308570000, P_GPLL6, 3.5, 0, 0),
1749 { P_XO, 0 },
1756 .cmd_rcgr = 0x5d000,
1770 F(24000000, P_XO, 1, 0, 0),
1771 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1772 F(100000000, P_GPLL0, 8, 0, 0),
1773 F(200000000, P_GPLL0, 4, 0, 0),
1778 .cmd_rcgr = 0x2902C,
1791 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1792 F(160000000, P_GPLL0, 5, 0, 0),
1793 F(300000000, P_GPLL4, 4, 0, 0),
1805 { P_XO, 0 },
1812 .cmd_rcgr = 0x29048,
1825 .cmd_rcgr = 0x3f020,
1839 .halt_reg = 0x1c020,
1841 .enable_reg = 0x1c020,
1842 .enable_mask = BIT(0),
1855 .halt_reg = 0x4601c,
1858 .enable_reg = 0x0b004,
1872 F(24000000, P_XO, 1, 0, 0),
1873 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1874 F(100000000, P_GPLL0, 8, 0, 0),
1875 F(133333333, P_GPLL0, 6, 0, 0),
1876 F(160000000, P_GPLL0, 5, 0, 0),
1877 F(200000000, P_GPLL0, 4, 0, 0),
1878 F(266666667, P_GPLL0, 3, 0, 0),
1883 .cmd_rcgr = 0x26004,
1896 F(24000000, P_XO, 1, 0, 0),
1897 F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1898 F(533333333, P_GPLL0, 1.5, 0, 0),
1911 { P_XO, 0 },
1918 .cmd_rcgr = 0x68088,
1931 .halt_reg = 0x46020,
1934 .enable_reg = 0x0b004,
1948 .halt_reg = 0x01008,
1951 .enable_reg = 0x0b004,
1965 .halt_reg = 0x02008,
1967 .enable_reg = 0x02008,
1968 .enable_mask = BIT(0),
1981 .halt_reg = 0x02004,
1983 .enable_reg = 0x02004,
1984 .enable_mask = BIT(0),
1997 .halt_reg = 0x03010,
1999 .enable_reg = 0x03010,
2000 .enable_mask = BIT(0),
2013 .halt_reg = 0x0300c,
2015 .enable_reg = 0x0300c,
2016 .enable_mask = BIT(0),
2029 .halt_reg = 0x04010,
2031 .enable_reg = 0x04010,
2032 .enable_mask = BIT(0),
2045 .halt_reg = 0x0400c,
2047 .enable_reg = 0x0400c,
2048 .enable_mask = BIT(0),
2061 .halt_reg = 0x05010,
2063 .enable_reg = 0x05010,
2064 .enable_mask = BIT(0),
2077 .halt_reg = 0x0500c,
2079 .enable_reg = 0x0500c,
2080 .enable_mask = BIT(0),
2093 .halt_reg = 0x06010,
2095 .enable_reg = 0x06010,
2096 .enable_mask = BIT(0),
2109 .halt_reg = 0x0600c,
2111 .enable_reg = 0x0600c,
2112 .enable_mask = BIT(0),
2125 .halt_reg = 0x0700c,
2127 .enable_reg = 0x0700c,
2128 .enable_mask = BIT(0),
2141 .halt_reg = 0x0203c,
2143 .enable_reg = 0x0203c,
2144 .enable_mask = BIT(0),
2157 .halt_reg = 0x0302c,
2159 .enable_reg = 0x0302c,
2160 .enable_mask = BIT(0),
2173 .halt_reg = 0x0402c,
2175 .enable_reg = 0x0402c,
2176 .enable_mask = BIT(0),
2189 .halt_reg = 0x0502c,
2191 .enable_reg = 0x0502c,
2192 .enable_mask = BIT(0),
2205 .halt_reg = 0x0602c,
2207 .enable_reg = 0x0602c,
2208 .enable_mask = BIT(0),
2221 .halt_reg = 0x0702c,
2223 .enable_reg = 0x0702c,
2224 .enable_mask = BIT(0),
2237 .halt_reg = 0x16024,
2240 .enable_reg = 0x0b004,
2241 .enable_mask = BIT(0),
2254 .halt_reg = 0x16020,
2257 .enable_reg = 0x0b004,
2271 .halt_reg = 0x1601c,
2274 .enable_reg = 0x0b004,
2301 .halt_reg = 0x30030,
2303 .enable_reg = 0x30030,
2304 .enable_mask = BIT(0),
2317 .halt_reg = 0x08000,
2319 .enable_reg = 0x08000,
2320 .enable_mask = BIT(0),
2333 .halt_reg = 0x09000,
2335 .enable_reg = 0x09000,
2336 .enable_mask = BIT(0),
2349 .halt_reg = 0x0a000,
2351 .enable_reg = 0x0a000,
2352 .enable_mask = BIT(0),
2365 .halt_reg = 0x58004,
2367 .enable_reg = 0x58004,
2368 .enable_mask = BIT(0),
2381 .halt_reg = 0x68310,
2383 .enable_reg = 0x68310,
2384 .enable_mask = BIT(0),
2397 .halt_reg = 0x68174,
2399 .enable_reg = 0x68174,
2400 .enable_mask = BIT(0),
2413 .halt_reg = 0x68170,
2415 .enable_reg = 0x68170,
2416 .enable_mask = BIT(0),
2429 .halt_reg = 0x68160,
2431 .enable_reg = 0x68160,
2432 .enable_mask = BIT(0),
2445 .halt_reg = 0x68164,
2447 .enable_reg = 0x68164,
2448 .enable_mask = BIT(0),
2461 .halt_reg = 0x68318,
2463 .enable_reg = 0x68318,
2464 .enable_mask = BIT(0),
2477 .halt_reg = 0x6819C,
2479 .enable_reg = 0x6819C,
2480 .enable_mask = BIT(0),
2493 .halt_reg = 0x68198,
2495 .enable_reg = 0x68198,
2496 .enable_mask = BIT(0),
2509 .halt_reg = 0x68168,
2511 .enable_reg = 0x68168,
2512 .enable_mask = BIT(0),
2525 .halt_reg = 0x2606c,
2527 .enable_reg = 0x2606c,
2528 .enable_mask = BIT(0),
2541 .halt_reg = 0x26070,
2543 .enable_reg = 0x26070,
2544 .enable_mask = BIT(0),
2557 F(24000000, P_XO, 1, 0, 0),
2558 F(133333333, P_GPLL0, 6, 0, 0),
2563 F(24000000, P_XO, 1, 0, 0),
2564 F(400000000, P_GPLL0, 2, 0, 0),
2569 .cmd_rcgr = 0x59020,
2590 { P_XO, 0 },
2598 .cmd_rcgr = 0x59120,
2611 F(24000000, P_XO, 1, 0, 0),
2612 F(100000000, P_GPLL0, 8, 0, 0),
2617 .cmd_rcgr = 0x1F020,
2630 F(24000000, P_XO, 1, 0, 0),
2631 F(266666667, P_GPLL0, 3, 0, 0),
2636 .cmd_rcgr = 0x1F040,
2649 F(24000000, P_XO, 1, 0, 0),
2650 F(400000000, P_GPLL0, 2, 0, 0),
2655 .cmd_rcgr = 0x1F008,
2668 F(24000000, P_XO, 1, 0, 0),
2669 F(50000000, P_GPLL0, 16, 0, 0),
2674 .cmd_rcgr = 0x3a00c,
2687 .halt_reg = 0x1F028,
2689 .enable_reg = 0x1F028,
2690 .enable_mask = BIT(0),
2703 .halt_reg = 0x1F048,
2705 .enable_reg = 0x1F048,
2706 .enable_mask = BIT(0),
2719 .halt_reg = 0x1F010,
2721 .enable_reg = 0x1F010,
2722 .enable_mask = BIT(0),
2735 .halt_reg = 0x1F018,
2737 .enable_reg = 0x1F018,
2738 .enable_mask = BIT(0),
2751 .halt_reg = 0x1F01C,
2753 .enable_reg = 0x1F01C,
2754 .enable_mask = BIT(0),
2767 .halt_reg = 0x1F014,
2769 .enable_reg = 0x1F014,
2770 .enable_mask = BIT(0),
2783 .halt_reg = 0x1F038,
2785 .enable_reg = 0x1F038,
2786 .enable_mask = BIT(0),
2799 .halt_reg = 0x12094,
2801 .enable_reg = 0xb00c,
2815 .halt_reg = 0x27020,
2817 .enable_reg = 0x27020,
2818 .enable_mask = BIT(0),
2831 .halt_reg = 0x1D044,
2833 .enable_reg = 0x1D044,
2834 .enable_mask = BIT(0),
2847 .halt_reg = 0x26074,
2849 .enable_reg = 0x26074,
2850 .enable_mask = BIT(0),
2863 .halt_reg = 0x1D03C,
2865 .enable_reg = 0x1D03C,
2866 .enable_mask = BIT(0),
2879 .halt_reg = 0x68240,
2881 .enable_reg = 0x68240,
2882 .enable_mask = BIT(0),
2895 .halt_reg = 0x68244,
2897 .enable_reg = 0x68244,
2898 .enable_mask = BIT(0),
2911 .halt_reg = 0x68248,
2913 .enable_reg = 0x68248,
2914 .enable_mask = BIT(0),
2927 .halt_reg = 0x6824c,
2929 .enable_reg = 0x6824c,
2930 .enable_mask = BIT(0),
2943 .halt_reg = 0x68250,
2945 .enable_reg = 0x68250,
2946 .enable_mask = BIT(0),
2959 .halt_reg = 0x68254,
2961 .enable_reg = 0x68254,
2962 .enable_mask = BIT(0),
2975 .halt_reg = 0x68258,
2977 .enable_reg = 0x68258,
2978 .enable_mask = BIT(0),
2991 .halt_reg = 0x6825c,
2993 .enable_reg = 0x6825c,
2994 .enable_mask = BIT(0),
3007 .halt_reg = 0x68260,
3009 .enable_reg = 0x68260,
3010 .enable_mask = BIT(0),
3023 .halt_reg = 0x68264,
3025 .enable_reg = 0x68264,
3026 .enable_mask = BIT(0),
3039 .halt_reg = 0x68194,
3041 .enable_reg = 0x68194,
3042 .enable_mask = BIT(0),
3055 .halt_reg = 0x68190,
3057 .enable_reg = 0x68190,
3058 .enable_mask = BIT(0),
3071 .halt_reg = 0x68338,
3073 .enable_reg = 0x68338,
3074 .enable_mask = BIT(0),
3087 .halt_reg = 0x6816C,
3089 .enable_reg = 0x6816C,
3090 .enable_mask = BIT(0),
3103 .halt_reg = 0x6830C,
3105 .enable_reg = 0x6830C,
3106 .enable_mask = BIT(0),
3119 .halt_reg = 0x68308,
3121 .enable_reg = 0x68308,
3122 .enable_mask = BIT(0),
3135 .halt_reg = 0x68314,
3137 .enable_reg = 0x68314,
3138 .enable_mask = BIT(0),
3151 .halt_reg = 0x68304,
3153 .enable_reg = 0x68304,
3154 .enable_mask = BIT(0),
3166 .halt_reg = 0x68300,
3168 .enable_reg = 0x68300,
3169 .enable_mask = BIT(0),
3182 .halt_reg = 0x68180,
3184 .enable_reg = 0x68180,
3185 .enable_mask = BIT(0),
3198 .halt_reg = 0x68188,
3200 .enable_reg = 0x68188,
3201 .enable_mask = BIT(0),
3214 .halt_reg = 0x68184,
3216 .enable_reg = 0x68184,
3217 .enable_mask = BIT(0),
3230 .halt_reg = 0x68270,
3232 .enable_reg = 0x68270,
3233 .enable_mask = BIT(0),
3246 .halt_reg = 0x68320,
3248 .enable_reg = 0x68320,
3249 .enable_mask = BIT(0),
3262 .halt_reg = 0x68324,
3264 .enable_reg = 0x68324,
3265 .enable_mask = BIT(0),
3278 .halt_reg = 0x68328,
3280 .enable_reg = 0x68328,
3281 .enable_mask = BIT(0),
3294 .halt_reg = 0x6832c,
3296 .enable_reg = 0x6832c,
3297 .enable_mask = BIT(0),
3310 .halt_reg = 0x68330,
3312 .enable_reg = 0x68330,
3313 .enable_mask = BIT(0),
3326 .halt_reg = 0x6820C,
3329 .enable_reg = 0x6820C,
3330 .enable_mask = BIT(0),
3343 .halt_reg = 0x68200,
3346 .enable_reg = 0x68200,
3347 .enable_mask = BIT(0),
3360 .halt_reg = 0x68204,
3363 .enable_reg = 0x68204,
3364 .enable_mask = BIT(0),
3377 .halt_reg = 0x68210,
3380 .enable_reg = 0x68210,
3381 .enable_mask = BIT(0),
3394 .halt_reg = 0x75010,
3396 .enable_reg = 0x75010,
3397 .enable_mask = BIT(0),
3410 .halt_reg = 0x75014,
3412 .enable_reg = 0x75014,
3413 .enable_mask = BIT(0),
3426 .halt_reg = 0x75008,
3428 .enable_reg = 0x75008,
3429 .enable_mask = BIT(0),
3442 .halt_reg = 0x7500c,
3444 .enable_reg = 0x7500c,
3445 .enable_mask = BIT(0),
3458 .halt_reg = 0x26048,
3460 .enable_reg = 0x26048,
3461 .enable_mask = BIT(0),
3474 .halt_reg = 0x75018,
3477 .enable_reg = 0x75018,
3478 .enable_mask = BIT(0),
3491 .halt_reg = 0x13004,
3494 .enable_reg = 0x0b004,
3508 .halt_reg = 0x29084,
3510 .enable_reg = 0x29084,
3511 .enable_mask = BIT(0),
3524 .halt_reg = 0x57024,
3526 .enable_reg = 0x57024,
3527 .enable_mask = BIT(0),
3540 .halt_reg = 0x57020,
3542 .enable_reg = 0x57020,
3543 .enable_mask = BIT(0),
3556 .halt_reg = 0x4201c,
3558 .enable_reg = 0x4201c,
3559 .enable_mask = BIT(0),
3572 .halt_reg = 0x42018,
3574 .enable_reg = 0x42018,
3575 .enable_mask = BIT(0),
3588 .halt_reg = 0x56008,
3590 .enable_reg = 0x56008,
3591 .enable_mask = BIT(0),
3604 .halt_reg = 0x56010,
3606 .enable_reg = 0x56010,
3607 .enable_mask = BIT(0),
3620 .halt_reg = 0x56014,
3622 .enable_reg = 0x56014,
3623 .enable_mask = BIT(0),
3636 .halt_reg = 0x56018,
3638 .enable_reg = 0x56018,
3639 .enable_mask = BIT(0),
3652 .halt_reg = 0x5601c,
3654 .enable_reg = 0x5601c,
3655 .enable_mask = BIT(0),
3668 .halt_reg = 0x56020,
3670 .enable_reg = 0x56020,
3671 .enable_mask = BIT(0),
3684 .halt_reg = 0x56024,
3686 .enable_reg = 0x56024,
3687 .enable_mask = BIT(0),
3700 .halt_reg = 0x56028,
3702 .enable_reg = 0x56028,
3703 .enable_mask = BIT(0),
3716 .halt_reg = 0x5602c,
3718 .enable_reg = 0x5602c,
3719 .enable_mask = BIT(0),
3732 .halt_reg = 0x56030,
3734 .enable_reg = 0x56030,
3735 .enable_mask = BIT(0),
3748 .halt_reg = 0x56034,
3750 .enable_reg = 0x56034,
3751 .enable_mask = BIT(0),
3764 .halt_reg = 0x5600C,
3766 .enable_reg = 0x5600C,
3767 .enable_mask = BIT(0),
3780 .halt_reg = 0x56108,
3782 .enable_reg = 0x56108,
3783 .enable_mask = BIT(0),
3796 .halt_reg = 0x56110,
3798 .enable_reg = 0x56110,
3799 .enable_mask = BIT(0),
3812 .halt_reg = 0x56114,
3814 .enable_reg = 0x56114,
3815 .enable_mask = BIT(0),
3828 .halt_reg = 0x5610C,
3830 .enable_reg = 0x5610C,
3831 .enable_mask = BIT(0),
3844 .halt_reg = 0x3e044,
3846 .enable_reg = 0x3e044,
3847 .enable_mask = BIT(0),
3860 .halt_reg = 0x3e000,
3862 .enable_reg = 0x3e000,
3863 .enable_mask = BIT(0),
3876 .halt_reg = 0x47014,
3878 .enable_reg = 0x47014,
3879 .enable_mask = BIT(0),
3892 .cmd_rcgr = 0x75070,
3905 .halt_reg = 0x75070,
3907 .enable_reg = 0x75070,
3921 .halt_reg = 0x75048,
3923 .enable_reg = 0x75048,
3924 .enable_mask = BIT(0),
3937 .halt_reg = 0x26040,
3939 .enable_reg = 0x26040,
3940 .enable_mask = BIT(0),
3953 .halt_reg = 0x3e008,
3955 .enable_reg = 0x3e008,
3956 .enable_mask = BIT(0),
3969 .halt_reg = 0x3e080,
3971 .enable_reg = 0x3e080,
3972 .enable_mask = BIT(0),
3985 .halt_reg = 0x3e040,
3988 .enable_reg = 0x3e040,
3989 .enable_mask = BIT(0),
4002 .halt_reg = 0x3e004,
4004 .enable_reg = 0x3e004,
4005 .enable_mask = BIT(0),
4018 .halt_reg = 0x3f000,
4020 .enable_reg = 0x3f000,
4021 .enable_mask = BIT(0),
4034 .halt_reg = 0x3f008,
4036 .enable_reg = 0x3f008,
4037 .enable_mask = BIT(0),
4050 .halt_reg = 0x3f080,
4052 .enable_reg = 0x3f080,
4053 .enable_mask = BIT(0),
4066 .halt_reg = 0x3f004,
4068 .enable_reg = 0x3f004,
4069 .enable_mask = BIT(0),
4082 .halt_reg = 0x56308,
4084 .enable_reg = 0x56308,
4085 .enable_mask = BIT(0),
4098 .halt_reg = 0x5630c,
4100 .enable_reg = 0x5630c,
4101 .enable_mask = BIT(0),
4114 .halt_reg = 0x5d014,
4116 .enable_reg = 0x5d014,
4117 .enable_mask = BIT(0),
4130 .halt_reg = 0x77004,
4132 .enable_reg = 0x77004,
4133 .enable_mask = BIT(0),
4146 .l = 0x3e,
4147 .alpha = 0x6667,
4148 .config_ctl_val = 0x240d4828,
4149 .config_ctl_hi_val = 0x6,
4150 .main_output_mask = BIT(0),
4152 .pre_div_val = 0x0,
4154 .post_div_val = 0x0,
4157 .test_ctl_val = 0x1C0000C0,
4158 .test_ctl_hi_val = 0x4000,
4162 .l = 0x32,
4163 .alpha = 0x0,
4164 .alpha_hi = 0x0,
4165 .config_ctl_val = 0x4001055b,
4166 .main_output_mask = BIT(0),
4167 .pre_div_val = 0x0,
4169 .post_div_val = 0x1 << 8,
4172 .vco_val = 0x0,
4409 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4410 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4411 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4412 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4413 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4414 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4415 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4416 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4417 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4418 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4419 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4420 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4421 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4422 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4423 [GCC_SMMU_BCR] = { 0x12000, 0 },
4424 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4425 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4426 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4427 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4428 [GCC_PRNG_BCR] = { 0x13000, 0 },
4429 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4430 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4431 [GCC_WCSS_BCR] = { 0x18000, 0 },
4432 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4433 [GCC_NSS_BCR] = { 0x19000, 0 },
4434 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4435 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4436 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4437 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4438 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4439 [GCC_TCSR_BCR] = { 0x28000, 0 },
4440 [GCC_QDSS_BCR] = { 0x29000, 0 },
4441 [GCC_DCD_BCR] = { 0x2a000, 0 },
4442 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4443 [GCC_MPM_BCR] = { 0x2c000, 0 },
4444 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4445 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4446 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4447 [GCC_TLMM_BCR] = { 0x34000, 0 },
4448 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4449 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4450 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4451 [GCC_USB0_BCR] = { 0x3e070, 0 },
4452 [GCC_USB1_BCR] = { 0x3f070, 0 },
4453 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4454 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4455 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4456 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4457 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4458 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4459 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4460 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4461 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4462 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4463 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4464 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4465 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4466 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4467 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4468 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4469 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4470 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4471 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4472 [GCC_QPIC_BCR] = { 0x57018, 0 },
4473 [GCC_MDIO_BCR] = { 0x58000, 0 },
4474 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4475 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4476 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4477 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4478 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4479 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4480 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4481 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4482 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4483 [GCC_DCC_BCR] = { 0x77000, 0 },
4484 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4485 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4486 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4487 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4488 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4489 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4490 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4491 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4492 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4493 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4494 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4495 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4496 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4497 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4498 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4499 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4500 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4501 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4502 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4503 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4504 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4505 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4506 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4507 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4508 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4509 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4510 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4511 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4512 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4513 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4514 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4515 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4516 [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4517 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4518 [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4519 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4520 [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4521 [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4522 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4523 [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4524 [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4525 [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4526 [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4527 [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4528 [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4529 [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4530 [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4531 [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4532 [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4533 [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4534 [GCC_LPASS_BCR] = {0x1F000, 0},
4535 [GCC_UBI32_TBU_BCR] = {0x65000, 0},
4536 [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4537 [GCC_WCSSAON_RESET] = {0x59010, 0},
4538 [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4539 [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4540 [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4541 [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4542 [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4543 [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4544 [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4545 [GCC_WCSS_DBG_ARES] = {0x59008, 0},
4546 [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4547 [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4548 [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4549 [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4550 [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4551 [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4552 [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4553 [GCC_Q6_AHB_ARES] = {0x59110, 2},
4554 [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4555 [GCC_Q6_AXIM_ARES] = {0x59110, 4},
4568 .max_register = 0x7fffc,
4591 regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); in gcc_ipq6018_probe()
4593 regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4595 regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); in gcc_ipq6018_probe()
4597 regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4600 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq6018_probe()