28 	u32 mask, val;  in clk_pll_enable()
68 	u32 mask;  in clk_pll_disable()
69 	u32 val;  in clk_pll_disable()
83 	u32 l, m, n, config;  in clk_pll_recalc_rate()
146 	u32 mode;  in clk_pll_set_rate()
147 	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;  in clk_pll_set_rate()
181 	u32 val;  in wait_for_pll()
221 	u32 val;  in clk_pll_configure()
222 	u32 mask;  in clk_pll_configure()
267 	u32 mode;  in clk_pll_sr2_enable()
306 	u32 mode;  in clk_pll_sr2_set_rate()
307 	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;  in clk_pll_sr2_set_rate()