Lines Matching refs:PWRCL_REG_OFFSET

78 #define PWRCL_REG_OFFSET 0x0  macro
132 	.offset = PWRCL_REG_OFFSET,
230 	.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
342 	.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
384 	.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
445 	regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc);  in qcom_cpu_clk_msm8996_register_clks()
451 	regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET,  in qcom_cpu_clk_msm8996_register_clks()
467 	regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET,  in qcom_cpu_clk_msm8996_register_clks()
478 	regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);  in qcom_cpu_clk_msm8996_register_clks()
482 	regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32);  in qcom_cpu_clk_msm8996_register_clks()
538 		regmap_write(regmap, PWRCL_REG_OFFSET + SSSCTL_OFFSET, 0xf);  in qcom_cpu_clk_msm8996_acd_init()