291 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,  in wait_for_pll()
294 	u32 val;  in wait_for_pll()
353 	u32 val, mask;  in clk_alpha_pll_configure()
411 	u32 val;  in clk_alpha_pll_hwfsm_enable()
436 	u32 val;  in clk_alpha_pll_hwfsm_disable()
462 static int pll_is_enabled(struct clk_hw *hw, u32 mask)  in pll_is_enabled()
466 	u32 val;  in pll_is_enabled()
489 	u32 val, mask;  in clk_alpha_pll_enable()
541 	u32 val, mask;  in clk_alpha_pll_disable()
565 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)  in alpha_pll_calc_rate()
571 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,  in alpha_pll_round_rate()
572 		     u32 alpha_width)  in alpha_pll_round_rate()
614 	u32 l, low, high, ctl;  in clk_alpha_pll_recalc_rate()
617 	u32 alpha_width = pll_alpha_width(pll);  in clk_alpha_pll_recalc_rate()
643 	u32 mode;  in __clk_alpha_pll_update_latch()
699 	u32 l, alpha_width = pll_alpha_width(pll);  in __clk_alpha_pll_set_rate()
750 	u32 l, alpha_width = pll_alpha_width(pll);  in clk_alpha_pll_round_rate()
765 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)  in alpha_huayra_pll_calc_rate()
779 			    u32 *l, u32 *a)  in alpha_huayra_pll_round_rate()
816 	u32 l, alpha = 0, ctl, alpha_m, alpha_n;  in alpha_pll_huayra_recalc_rate()
869 	u32 l, a, ctl, cur_alpha = 0;  in alpha_pll_huayra_set_rate()
911 	u32 l, a;  in alpha_pll_huayra_round_rate()
919 	u32 mode_val, opmode_val;  in trion_pll_is_enabled()
941 	u32 val;  in clk_trion_pll_enable()
978 	u32 val;  in clk_trion_pll_disable()
1011 	u32 l, frac, alpha_width = pll_alpha_width(pll);  in clk_trion_pll_recalc_rate()
1070 	u32 ctl;  in clk_alpha_pll_postdiv_recalc_rate()
1117 	u32 ctl, div;  in clk_alpha_pll_postdiv_round_ro_rate()
1161 	u32 val, mask;  in clk_fabia_pll_configure()
1199 	u32 val, opmode_val;  in alpha_pll_fabia_enable()
1256 	u32 val;  in alpha_pll_fabia_disable()
1286 	u32 l, frac, alpha_width = pll_alpha_width(pll);  in alpha_pll_fabia_recalc_rate()
1316 	u32 l, alpha_width = pll_alpha_width(pll);  in alpha_pll_fabia_set_rate()
1339 	u32 cal_l, val, alpha_width = pll_alpha_width(pll);  in alpha_pll_fabia_prepare()
1412 	u32 i, div = 1, val;  in clk_alpha_pll_postdiv_fabia_recalc_rate()
1437 	u32 i, div = 1, val;  in clk_trion_pll_postdiv_recalc_rate()
1597 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)  in __alpha_pll_trion_prepare()
1600 	u32 val;  in __alpha_pll_trion_prepare()
1627 				      unsigned long prate, u32 latch_bit, u32 latch_ack)  in __alpha_pll_trion_set_rate()
1631 	u32 val, l, alpha_width = pll_alpha_width(pll);  in __alpha_pll_trion_set_rate()
1730 	u32 l, alpha_width = pll_alpha_width(pll);  in clk_alpha_pll_agera_set_rate()
1815 	u32 val;  in alpha_pll_lucid_5lpe_enable()
1857 	u32 val;  in alpha_pll_lucid_5lpe_disable()
1892 	u32 val = 0;  in alpha_pll_lucid_5lpe_prepare()
1928 	u32 mask;  in __clk_lucid_pll_postdiv_set_rate()
2025 	u32 val;  in clk_zonda_pll_enable()
2075 	u32 val;  in clk_zonda_pll_disable()
2103 	u32 test_ctl_val;  in clk_zonda_pll_set_rate()
2104 	u32 l, alpha_width = pll_alpha_width(pll);  in clk_zonda_pll_set_rate()
2149 	u32 lval = config->l;  in clk_lucid_evo_pll_configure()
2177 	u32 val;  in alpha_pll_lucid_evo_enable()
2231 	u32 val;  in _alpha_pll_lucid_evo_disable()
2265 	u32 val = 0;  in _alpha_pll_lucid_evo_prepare()
2311 	u32 l, frac;  in alpha_pll_lucid_evo_recalc_rate()
2388 	u32 l;  in clk_rivian_evo_pll_recalc_rate()
2400 	u32 l;  in clk_rivian_evo_pll_round_rate()
2425 	u32 val, val_u, mask, mask_u;  in clk_stromer_pll_configure()
2479 	u32 l;  in clk_alpha_pll_stromer_determine_rate()
2493 	u32 l;  in clk_alpha_pll_stromer_set_rate()
2541 	u32 l, alpha_width = pll_alpha_width(pll);  in clk_alpha_pll_stromer_plus_set_rate()