Lines Matching +full:pll +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
22 # define PLL_LOCK_COUNT_MASK 0x3f
24 # define PLL_BIAS_COUNT_MASK 0x3f
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
47 # define PLL_VCO_MASK 0x3
49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
59 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
60 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
61 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
65 [PLL_OFF_L_VAL] = 0x04,
66 [PLL_OFF_ALPHA_VAL] = 0x08,
67 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
68 [PLL_OFF_USER_CTL] = 0x10,
69 [PLL_OFF_USER_CTL_U] = 0x14,
70 [PLL_OFF_CONFIG_CTL] = 0x18,
71 [PLL_OFF_TEST_CTL] = 0x1c,
72 [PLL_OFF_TEST_CTL_U] = 0x20,
73 [PLL_OFF_STATUS] = 0x24,
76 [PLL_OFF_L_VAL] = 0x04,
77 [PLL_OFF_ALPHA_VAL] = 0x08,
78 [PLL_OFF_USER_CTL] = 0x10,
79 [PLL_OFF_CONFIG_CTL] = 0x14,
80 [PLL_OFF_CONFIG_CTL_U] = 0x18,
81 [PLL_OFF_TEST_CTL] = 0x1c,
82 [PLL_OFF_TEST_CTL_U] = 0x20,
83 [PLL_OFF_STATUS] = 0x24,
86 [PLL_OFF_L_VAL] = 0x04,
87 [PLL_OFF_ALPHA_VAL] = 0x08,
88 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
89 [PLL_OFF_USER_CTL] = 0x10,
90 [PLL_OFF_CONFIG_CTL] = 0x18,
91 [PLL_OFF_TEST_CTL] = 0x1c,
92 [PLL_OFF_STATUS] = 0x24,
95 [PLL_OFF_L_VAL] = 0x04,
96 [PLL_OFF_USER_CTL] = 0x0c,
97 [PLL_OFF_USER_CTL_U] = 0x10,
98 [PLL_OFF_CONFIG_CTL] = 0x14,
99 [PLL_OFF_CONFIG_CTL_U] = 0x18,
100 [PLL_OFF_TEST_CTL] = 0x1c,
101 [PLL_OFF_TEST_CTL_U] = 0x20,
102 [PLL_OFF_STATUS] = 0x24,
103 [PLL_OFF_OPMODE] = 0x2c,
104 [PLL_OFF_FRAC] = 0x38,
107 [PLL_OFF_L_VAL] = 0x04,
108 [PLL_OFF_CAL_L_VAL] = 0x08,
109 [PLL_OFF_USER_CTL] = 0x0c,
110 [PLL_OFF_USER_CTL_U] = 0x10,
111 [PLL_OFF_USER_CTL_U1] = 0x14,
112 [PLL_OFF_CONFIG_CTL] = 0x18,
113 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
114 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
115 [PLL_OFF_TEST_CTL] = 0x24,
116 [PLL_OFF_TEST_CTL_U] = 0x28,
117 [PLL_OFF_TEST_CTL_U1] = 0x2c,
118 [PLL_OFF_STATUS] = 0x30,
119 [PLL_OFF_OPMODE] = 0x38,
120 [PLL_OFF_ALPHA_VAL] = 0x40,
123 [PLL_OFF_L_VAL] = 0x04,
124 [PLL_OFF_ALPHA_VAL] = 0x08,
125 [PLL_OFF_USER_CTL] = 0x0c,
126 [PLL_OFF_CONFIG_CTL] = 0x10,
127 [PLL_OFF_CONFIG_CTL_U] = 0x14,
128 [PLL_OFF_TEST_CTL] = 0x18,
129 [PLL_OFF_TEST_CTL_U] = 0x1c,
130 [PLL_OFF_STATUS] = 0x2c,
133 [PLL_OFF_L_VAL] = 0x04,
134 [PLL_OFF_ALPHA_VAL] = 0x08,
135 [PLL_OFF_USER_CTL] = 0x0c,
136 [PLL_OFF_CONFIG_CTL] = 0x10,
137 [PLL_OFF_CONFIG_CTL_U] = 0x14,
138 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
139 [PLL_OFF_TEST_CTL] = 0x1c,
140 [PLL_OFF_TEST_CTL_U] = 0x20,
141 [PLL_OFF_TEST_CTL_U1] = 0x24,
142 [PLL_OFF_OPMODE] = 0x28,
143 [PLL_OFF_STATUS] = 0x38,
146 [PLL_OFF_OPMODE] = 0x04,
147 [PLL_OFF_STATUS] = 0x0c,
148 [PLL_OFF_L_VAL] = 0x10,
149 [PLL_OFF_ALPHA_VAL] = 0x14,
150 [PLL_OFF_USER_CTL] = 0x18,
151 [PLL_OFF_USER_CTL_U] = 0x1c,
152 [PLL_OFF_CONFIG_CTL] = 0x20,
153 [PLL_OFF_CONFIG_CTL_U] = 0x24,
154 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
155 [PLL_OFF_TEST_CTL] = 0x2c,
156 [PLL_OFF_TEST_CTL_U] = 0x30,
157 [PLL_OFF_TEST_CTL_U1] = 0x34,
160 [PLL_OFF_OPMODE] = 0x04,
161 [PLL_OFF_STATE] = 0x08,
162 [PLL_OFF_STATUS] = 0x0c,
163 [PLL_OFF_L_VAL] = 0x10,
164 [PLL_OFF_ALPHA_VAL] = 0x14,
165 [PLL_OFF_USER_CTL] = 0x18,
166 [PLL_OFF_USER_CTL_U] = 0x1c,
167 [PLL_OFF_CONFIG_CTL] = 0x20,
168 [PLL_OFF_CONFIG_CTL_U] = 0x24,
169 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
170 [PLL_OFF_TEST_CTL] = 0x2c,
171 [PLL_OFF_TEST_CTL_U] = 0x30,
172 [PLL_OFF_TEST_CTL_U1] = 0x34,
173 [PLL_OFF_TEST_CTL_U2] = 0x38,
176 [PLL_OFF_OPMODE] = 0x04,
177 [PLL_OFF_STATUS] = 0x0c,
178 [PLL_OFF_L_VAL] = 0x10,
179 [PLL_OFF_USER_CTL] = 0x14,
180 [PLL_OFF_USER_CTL_U] = 0x18,
181 [PLL_OFF_CONFIG_CTL] = 0x1c,
182 [PLL_OFF_CONFIG_CTL_U] = 0x20,
183 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
184 [PLL_OFF_TEST_CTL] = 0x28,
185 [PLL_OFF_TEST_CTL_U] = 0x2c,
188 [PLL_OFF_L_VAL] = 0x04,
189 [PLL_OFF_ALPHA_VAL] = 0x08,
190 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
191 [PLL_OFF_TEST_CTL] = 0x10,
192 [PLL_OFF_TEST_CTL_U] = 0x14,
193 [PLL_OFF_USER_CTL] = 0x18,
194 [PLL_OFF_USER_CTL_U] = 0x1c,
195 [PLL_OFF_CONFIG_CTL] = 0x20,
196 [PLL_OFF_STATUS] = 0x24,
199 [PLL_OFF_L_VAL] = 0x04,
200 [PLL_OFF_ALPHA_VAL] = 0x08,
201 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
202 [PLL_OFF_TEST_CTL] = 0x10,
203 [PLL_OFF_TEST_CTL_U] = 0x14,
204 [PLL_OFF_USER_CTL] = 0x18,
205 [PLL_OFF_CONFIG_CTL] = 0x1C,
206 [PLL_OFF_STATUS] = 0x20,
209 [PLL_OFF_L_VAL] = 0x08,
210 [PLL_OFF_ALPHA_VAL] = 0x10,
211 [PLL_OFF_ALPHA_VAL_U] = 0x14,
212 [PLL_OFF_USER_CTL] = 0x18,
213 [PLL_OFF_USER_CTL_U] = 0x1c,
214 [PLL_OFF_CONFIG_CTL] = 0x20,
215 [PLL_OFF_TEST_CTL] = 0x30,
216 [PLL_OFF_TEST_CTL_U] = 0x34,
217 [PLL_OFF_STATUS] = 0x28,
220 [PLL_OFF_L_VAL] = 0x04,
221 [PLL_OFF_USER_CTL] = 0x08,
222 [PLL_OFF_USER_CTL_U] = 0x0c,
223 [PLL_OFF_CONFIG_CTL] = 0x10,
224 [PLL_OFF_TEST_CTL] = 0x14,
225 [PLL_OFF_TEST_CTL_U] = 0x18,
226 [PLL_OFF_STATUS] = 0x1c,
227 [PLL_OFF_ALPHA_VAL] = 0x24,
228 [PLL_OFF_ALPHA_VAL_U] = 0x28,
245 #define PLL_HUAYRA_M_MASK 0xff
246 #define PLL_HUAYRA_N_SHIFT 0
247 #define PLL_HUAYRA_N_MASK 0xff
250 #define PLL_STANDBY 0x0
251 #define PLL_RUN 0x1
252 #define PLL_OUT_MASK 0x7
255 /* TRION PLL specific settings and offsets */
256 #define TRION_PLL_CAL_VAL 0x44
259 /* LUCID PLL specific settings and offsets */
262 /* LUCID 5LPE PLL specific settings and offsets */
268 /* LUCID EVO PLL specific settings and offsets */
271 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
274 /* ZONDA PLL specific */
275 #define ZONDA_PLL_OUT_MASK 0xf
280 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
283 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
291 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
297 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
299 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
303 for (count = 200; count > 0; count--) { in wait_for_pll()
304 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
308 return 0; in wait_for_pll()
310 return 0; in wait_for_pll()
316 return -ETIMEDOUT; in wait_for_pll()
319 #define wait_for_pll_enable_active(pll) \ argument
320 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
322 #define wait_for_pll_enable_lock(pll) \ argument
323 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
325 #define wait_for_zonda_pll_freq_lock(pll) \ argument
326 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
328 #define wait_for_pll_disable(pll) \ argument
329 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
331 #define wait_for_pll_offline(pll) \ argument
332 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
334 #define wait_for_pll_update(pll) \ argument
335 wait_for_pll(pll, PLL_UPDATE, 1, "update")
337 #define wait_for_pll_update_ack_set(pll) \ argument
338 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
340 #define wait_for_pll_update_ack_clear(pll) \ argument
341 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
350 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
355 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
356 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
357 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
359 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
360 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
361 config->config_ctl_hi_val); in clk_alpha_pll_configure()
363 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
364 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
366 val = config->main_output_mask; in clk_alpha_pll_configure()
367 val |= config->aux_output_mask; in clk_alpha_pll_configure()
368 val |= config->aux2_output_mask; in clk_alpha_pll_configure()
369 val |= config->early_output_mask; in clk_alpha_pll_configure()
370 val |= config->pre_div_val; in clk_alpha_pll_configure()
371 val |= config->post_div_val; in clk_alpha_pll_configure()
372 val |= config->vco_val; in clk_alpha_pll_configure()
373 val |= config->alpha_en_mask; in clk_alpha_pll_configure()
374 val |= config->alpha_mode_mask; in clk_alpha_pll_configure()
376 mask = config->main_output_mask; in clk_alpha_pll_configure()
377 mask |= config->aux_output_mask; in clk_alpha_pll_configure()
378 mask |= config->aux2_output_mask; in clk_alpha_pll_configure()
379 mask |= config->early_output_mask; in clk_alpha_pll_configure()
380 mask |= config->pre_div_mask; in clk_alpha_pll_configure()
381 mask |= config->post_div_mask; in clk_alpha_pll_configure()
382 mask |= config->vco_mask; in clk_alpha_pll_configure()
384 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
386 if (config->test_ctl_mask) in clk_alpha_pll_configure()
387 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
388 config->test_ctl_mask, in clk_alpha_pll_configure()
389 config->test_ctl_val); in clk_alpha_pll_configure()
391 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
392 config->test_ctl_val); in clk_alpha_pll_configure()
394 if (config->test_ctl_hi_mask) in clk_alpha_pll_configure()
395 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
396 config->test_ctl_hi_mask, in clk_alpha_pll_configure()
397 config->test_ctl_hi_val); in clk_alpha_pll_configure()
399 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
400 config->test_ctl_hi_val); in clk_alpha_pll_configure()
402 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
403 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
410 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
413 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
419 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
422 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
429 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
435 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
438 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
442 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
443 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
448 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
454 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
455 PLL_FSM_ENA, 0); in clk_alpha_pll_hwfsm_disable()
459 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
465 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
468 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
488 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
492 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
501 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
506 return 0; in clk_alpha_pll_enable()
508 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
515 * de-asserting the reset. in clk_alpha_pll_enable()
520 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
525 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
529 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
543 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
554 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
561 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
582 *a = 0; in alpha_pll_round_rate()
599 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
601 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
602 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
605 if (rate >= v->min_freq && rate <= v->max_freq) in alpha_pll_find_vco()
615 u64 a = 0, prate = parent_rate; in clk_alpha_pll_recalc_rate()
616 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
617 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
619 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
621 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
623 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
625 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
629 a = low & GENMASK(alpha_width - 1, 0); in clk_alpha_pll_recalc_rate()
633 a >>= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_recalc_rate()
640 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
645 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
647 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
648 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
655 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
656 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
657 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
659 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
662 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
666 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
668 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
673 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
677 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
680 return 0; in __clk_alpha_pll_update_latch()
683 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
686 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
687 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
688 return 0; in clk_alpha_pll_update_latch()
690 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
697 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
699 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
703 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
704 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
705 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
707 return -EINVAL; in __clk_alpha_pll_set_rate()
710 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
713 a <<= alpha_width - ALPHA_BITWIDTH; in __clk_alpha_pll_set_rate()
716 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
718 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
721 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
723 vco->val << PLL_VCO_SHIFT); in __clk_alpha_pll_set_rate()
726 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
729 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
749 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
750 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
755 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
758 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
759 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
769 * of [-0.5, 0.5). in alpha_huayra_pll_calc_rate()
771 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_calc_rate()
772 l -= 1; in alpha_huayra_pll_calc_rate()
789 *a = 0; in alpha_huayra_pll_round_rate()
801 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value in alpha_huayra_pll_round_rate()
804 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_round_rate()
815 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
816 u32 l, alpha = 0, ctl, alpha_m, alpha_n; in alpha_pll_huayra_recalc_rate()
818 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
819 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
822 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
826 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N in alpha_pll_huayra_recalc_rate()
830 * M is a signed number (-128 to 127) and N is unsigned in alpha_pll_huayra_recalc_rate()
831 * (0 to 255). M/N has to be within +/-0.5. in alpha_pll_huayra_recalc_rate()
833 * When alpha_mode=0, it is a two’s complement number in the in alpha_pll_huayra_recalc_rate()
834 * range [-0.5, 0.5). in alpha_pll_huayra_recalc_rate()
848 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { in alpha_pll_huayra_recalc_rate()
849 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; in alpha_pll_huayra_recalc_rate()
852 rate -= tmp; in alpha_pll_huayra_recalc_rate()
868 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
869 u32 l, a, ctl, cur_alpha = 0; in alpha_pll_huayra_set_rate()
873 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
876 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
879 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
886 return -EBUSY; in alpha_pll_huayra_set_rate()
889 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
892 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
895 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
896 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
898 if (a == 0) in alpha_pll_huayra_set_rate()
899 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
900 PLL_ALPHA_EN, 0x0); in alpha_pll_huayra_set_rate()
902 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
905 return 0; in alpha_pll_huayra_set_rate()
916 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
922 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
923 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
925 return 0; in trion_pll_is_enabled()
932 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
934 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
939 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
940 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
944 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
953 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
957 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
959 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
963 /* Enable the PLL outputs */ in clk_trion_pll_enable()
964 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
969 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
970 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
976 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
977 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
981 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
991 /* Disable the global PLL output */ in clk_trion_pll_disable()
992 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
996 /* Disable the PLL outputs */ in clk_trion_pll_disable()
997 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
998 PLL_OUT_MASK, 0); in clk_trion_pll_disable()
1002 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1003 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1004 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1010 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1011 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1013 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
1014 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
1069 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1072 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
1075 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1081 { 0x0, 1 },
1082 { 0x1, 2 },
1083 { 0x3, 4 },
1084 { 0x7, 8 },
1085 { 0xf, 16 },
1090 { 0x0, 1 },
1091 { 0x1, 2 },
1092 { 0x3, 4 },
1100 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1103 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1109 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1116 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1119 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1122 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1134 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1137 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ in clk_alpha_pll_postdiv_set_rate()
1138 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; in clk_alpha_pll_postdiv_set_rate()
1140 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1141 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1158 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1163 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1164 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1165 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1166 config->config_ctl_val); in clk_fabia_pll_configure()
1167 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1168 config->config_ctl_hi_val); in clk_fabia_pll_configure()
1169 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1170 config->user_ctl_val); in clk_fabia_pll_configure()
1171 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1172 config->user_ctl_hi_val); in clk_fabia_pll_configure()
1173 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1174 config->test_ctl_val); in clk_fabia_pll_configure()
1175 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1176 config->test_ctl_hi_val); in clk_fabia_pll_configure()
1178 if (config->post_div_mask) { in clk_fabia_pll_configure()
1179 mask = config->post_div_mask; in clk_fabia_pll_configure()
1180 val = config->post_div_val; in clk_fabia_pll_configure()
1181 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1184 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1185 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1188 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1191 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1198 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1200 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1202 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1211 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1214 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1218 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1220 return 0; in alpha_pll_fabia_enable()
1222 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1226 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1230 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1235 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1239 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1243 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1248 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1255 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1257 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1259 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1269 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1274 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1278 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1279 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1285 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1286 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1288 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1289 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1306 return -EINVAL; in alpha_pll_check_rate_margin()
1309 return 0; in alpha_pll_check_rate_margin()
1315 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1316 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1324 if (ret < 0) in alpha_pll_fabia_set_rate()
1327 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1328 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1330 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1335 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1339 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1344 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1345 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1351 return 0; in alpha_pll_fabia_prepare()
1353 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1355 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1356 return -EINVAL; in alpha_pll_fabia_prepare()
1359 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1360 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1364 return -EINVAL; in alpha_pll_fabia_prepare()
1370 if (ret < 0) in alpha_pll_fabia_prepare()
1373 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1374 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1376 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1379 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1385 return 0; in alpha_pll_fabia_prepare()
1411 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1415 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1419 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1420 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1422 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1423 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1424 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1435 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1436 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1439 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1441 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1442 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1444 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1445 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1446 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1458 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1460 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1461 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1468 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1469 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1470 int i, val = 0, div; in clk_trion_pll_postdiv_set_rate()
1473 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1474 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1475 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1480 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1481 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, in clk_trion_pll_postdiv_set_rate()
1482 val << pll->post_div_shift); in clk_trion_pll_postdiv_set_rate()
1495 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1497 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1498 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1504 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1505 int i, val = 0, div, ret; in clk_alpha_pll_postdiv_fabia_set_rate()
1508 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1509 * no-operation. in clk_alpha_pll_postdiv_fabia_set_rate()
1511 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1516 return 0; in clk_alpha_pll_postdiv_fabia_set_rate()
1519 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1520 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1521 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1526 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1527 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1528 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1539 * clk_trion_pll_configure - configure the trion pll
1541 * @pll: clk alpha pll
1543 * @config: configuration to apply for pll
1545 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1549 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1550 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1552 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1553 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1557 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1558 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1559 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1560 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1561 config->config_ctl_val); in clk_trion_pll_configure()
1562 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1563 config->config_ctl_hi_val); in clk_trion_pll_configure()
1564 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1565 config->config_ctl_hi1_val); in clk_trion_pll_configure()
1566 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1567 config->user_ctl_val); in clk_trion_pll_configure()
1568 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1569 config->user_ctl_hi_val); in clk_trion_pll_configure()
1570 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1571 config->user_ctl_hi1_val); in clk_trion_pll_configure()
1572 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1573 config->test_ctl_val); in clk_trion_pll_configure()
1574 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1575 config->test_ctl_hi_val); in clk_trion_pll_configure()
1576 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1577 config->test_ctl_hi1_val); in clk_trion_pll_configure()
1579 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1582 /* Disable PLL output */ in clk_trion_pll_configure()
1583 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1586 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1588 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1589 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1594 * The TRION PLL requires a power-on self-calibration which happens when the
1595 * PLL comes out of reset. Calibrate in case it is not completed.
1599 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1604 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1606 return 0; in __alpha_pll_trion_prepare()
1629 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1631 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1638 if (ret < 0) in __alpha_pll_trion_set_rate()
1641 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); in __alpha_pll_trion_set_rate()
1642 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1644 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1645 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1651 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1653 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1654 return -EINVAL; in __alpha_pll_trion_set_rate()
1657 /* Return the latch input to 0 */ in __alpha_pll_trion_set_rate()
1658 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1663 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1668 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1670 return 0; in __alpha_pll_trion_set_rate()
1708 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1711 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1712 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1713 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1714 config->user_ctl_val); in clk_agera_pll_configure()
1715 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1716 config->config_ctl_val); in clk_agera_pll_configure()
1717 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1718 config->config_ctl_hi_val); in clk_agera_pll_configure()
1719 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1720 config->test_ctl_val); in clk_agera_pll_configure()
1721 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1722 config->test_ctl_hi_val); in clk_agera_pll_configure()
1729 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1730 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1737 if (ret < 0) in clk_alpha_pll_agera_set_rate()
1741 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1742 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1745 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1747 return 0; in clk_alpha_pll_agera_set_rate()
1761 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1763 * @pll: clk alpha pll
1765 * @config: configuration to apply for pll
1767 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_5lpe_pll_configure() argument
1771 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_5lpe_pll_configure()
1772 * RCGs that will lock up if we disable the PLL below. in clk_lucid_5lpe_pll_configure()
1774 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_5lpe_pll_configure()
1775 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); in clk_lucid_5lpe_pll_configure()
1779 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_lucid_5lpe_pll_configure()
1780 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_lucid_5lpe_pll_configure()
1781 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_5lpe_pll_configure()
1782 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_lucid_5lpe_pll_configure()
1783 config->config_ctl_val); in clk_lucid_5lpe_pll_configure()
1784 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1785 config->config_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1786 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1787 config->config_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1788 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_configure()
1789 config->user_ctl_val); in clk_lucid_5lpe_pll_configure()
1790 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1791 config->user_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1792 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1793 config->user_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1794 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_lucid_5lpe_pll_configure()
1795 config->test_ctl_val); in clk_lucid_5lpe_pll_configure()
1796 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1797 config->test_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1798 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1799 config->test_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1801 /* Disable PLL output */ in clk_lucid_5lpe_pll_configure()
1802 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_5lpe_pll_configure()
1805 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_5lpe_pll_configure()
1807 /* Place the PLL in STANDBY mode */ in clk_lucid_5lpe_pll_configure()
1808 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_5lpe_pll_configure()
1814 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1818 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1827 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1830 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1831 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); in alpha_pll_lucid_5lpe_enable()
1832 if (ret < 0) in alpha_pll_lucid_5lpe_enable()
1835 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1839 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1841 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1845 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1846 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1850 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1851 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1856 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1860 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1870 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1871 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
1875 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
1876 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
1880 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
1881 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
1885 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1886 * when the PLL comes out of reset. Calibrate in case it is not completed.
1890 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
1892 u32 val = 0; in alpha_pll_lucid_5lpe_prepare()
1896 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
1898 return 0; in alpha_pll_lucid_5lpe_prepare()
1902 return -EINVAL; in alpha_pll_lucid_5lpe_prepare()
1910 return 0; in alpha_pll_lucid_5lpe_prepare()
1925 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
1926 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
1931 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
1932 * no-operation. in __clk_lucid_pll_postdiv_set_rate()
1934 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
1939 return 0; in __clk_lucid_pll_postdiv_set_rate()
1941 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
1942 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
1943 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
1944 return -EINVAL; in __clk_lucid_pll_postdiv_set_rate()
1948 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
1949 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
1950 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
1955 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1956 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
1957 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
1993 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
1996 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
1997 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
1998 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
1999 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
2000 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
2001 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
2002 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
2003 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
2004 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
2005 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
2006 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
2008 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
2010 /* Disable PLL output */ in clk_zonda_pll_configure()
2011 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
2014 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
2016 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
2017 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
2023 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
2024 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
2028 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
2035 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
2038 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
2039 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2043 * de-asserting the reset. in clk_zonda_pll_enable()
2047 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
2050 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2052 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2056 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2058 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2062 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2063 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2065 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2066 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2068 return 0; in clk_zonda_pll_enable()
2073 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2074 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2077 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2085 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2086 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2088 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2089 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2091 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2092 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2094 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2095 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2101 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2104 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2111 if (ret < 0) in clk_zonda_pll_set_rate()
2114 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2115 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2121 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2125 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2127 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2131 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2133 return 0; in clk_zonda_pll_set_rate()
2146 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2149 u32 lval = config->l; in clk_lucid_evo_pll_configure()
2152 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2153 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2154 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2155 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2156 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2157 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2158 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2159 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2160 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2161 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2162 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2164 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2165 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2167 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_evo_pll_configure()
2168 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2169 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2175 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2176 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2180 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2189 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2192 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2193 ret = trion_pll_is_enabled(pll, regmap); in alpha_pll_lucid_evo_enable()
2194 if (ret < 0) { in alpha_pll_lucid_evo_enable()
2197 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); in alpha_pll_lucid_evo_enable()
2198 return 0; in alpha_pll_lucid_evo_enable()
2201 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2206 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2208 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2212 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2213 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2217 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2218 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2229 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2230 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2234 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2244 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2245 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2249 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2250 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2254 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2255 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2258 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2263 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2265 u32 val = 0; in _alpha_pll_lucid_evo_prepare()
2269 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2271 return 0; in _alpha_pll_lucid_evo_prepare()
2275 return -EINVAL; in _alpha_pll_lucid_evo_prepare()
2283 return 0; in _alpha_pll_lucid_evo_prepare()
2309 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2310 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2313 regmap_read(regmap, PLL_L_VAL(pll), &l); in alpha_pll_lucid_evo_recalc_rate()
2315 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); in alpha_pll_lucid_evo_recalc_rate()
2317 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2364 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2367 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2368 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2369 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2370 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2371 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2372 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2373 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2374 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2376 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2378 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2387 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2390 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_rivian_evo_pll_recalc_rate()
2398 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2403 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); in clk_rivian_evo_pll_round_rate()
2404 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2407 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2408 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()
2422 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2427 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2428 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2429 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2431 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2432 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2433 config->config_ctl_hi_val); in clk_stromer_pll_configure()
2435 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2436 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2438 val = config->main_output_mask; in clk_stromer_pll_configure()
2439 val |= config->aux_output_mask; in clk_stromer_pll_configure()
2440 val |= config->aux2_output_mask; in clk_stromer_pll_configure()
2441 val |= config->early_output_mask; in clk_stromer_pll_configure()
2442 val |= config->pre_div_val; in clk_stromer_pll_configure()
2443 val |= config->post_div_val; in clk_stromer_pll_configure()
2444 val |= config->vco_val; in clk_stromer_pll_configure()
2445 val |= config->alpha_en_mask; in clk_stromer_pll_configure()
2446 val |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2448 mask = config->main_output_mask; in clk_stromer_pll_configure()
2449 mask |= config->aux_output_mask; in clk_stromer_pll_configure()
2450 mask |= config->aux2_output_mask; in clk_stromer_pll_configure()
2451 mask |= config->early_output_mask; in clk_stromer_pll_configure()
2452 mask |= config->pre_div_mask; in clk_stromer_pll_configure()
2453 mask |= config->post_div_mask; in clk_stromer_pll_configure()
2454 mask |= config->vco_mask; in clk_stromer_pll_configure()
2455 mask |= config->alpha_en_mask; in clk_stromer_pll_configure()
2456 mask |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2458 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2460 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2461 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; in clk_stromer_pll_configure()
2462 val_u |= config->lock_det; in clk_stromer_pll_configure()
2464 mask_u = config->status_mask; in clk_stromer_pll_configure()
2465 mask_u |= config->lock_det; in clk_stromer_pll_configure()
2467 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2468 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2469 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2471 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2472 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2482 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, in clk_alpha_pll_stromer_determine_rate()
2485 return 0; in clk_alpha_pll_stromer_determine_rate()
2491 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2498 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2500 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_set_rate()
2501 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2502 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2505 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2509 return 0; in clk_alpha_pll_stromer_set_rate()
2512 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2513 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2516 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2519 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2523 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2541 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2547 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2551 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2556 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2559 a <<= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_plus_set_rate()
2561 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2562 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2565 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_plus_set_rate()
2568 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2572 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2578 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2580 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2586 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()
2589 return 0; in clk_alpha_pll_stromer_plus_set_rate()