Lines Matching +full:0 +full:x9038
36 { 249600000, 2000000000, 0 },
41 .l = 0x1f,
42 .alpha = 0x4000,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00002067,
45 .test_ctl_val = 0x40000000,
46 .test_ctl_hi_val = 0x00000002,
47 .user_ctl_val = 0x00000101,
48 .user_ctl_hi_val = 0x00004805,
52 .offset = 0x0,
69 { 0x1, 2 },
74 .offset = 0x0,
93 .l = 0x2a,
94 .alpha = 0x1555,
95 .config_ctl_val = 0x20485699,
96 .config_ctl_hi_val = 0x00002067,
97 .test_ctl_val = 0x40000000,
98 .test_ctl_hi_val = 0x00000000,
99 .user_ctl_val = 0x00000101,
100 .user_ctl_hi_val = 0x00004805,
104 .offset = 0x1000,
121 { 0x1, 2 },
126 .offset = 0x1000,
145 .l = 0x64,
146 .alpha = 0x0,
147 .post_div_val = 0x3 << 8,
148 .post_div_mask = 0x3 << 8,
150 .main_output_mask = BIT(0),
152 .config_ctl_val = 0x20000800,
153 .config_ctl_hi_val = 0x400003d2,
154 .test_ctl_val = 0x04000400,
155 .test_ctl_hi_val = 0x00004000,
159 .offset = 0x2000,
187 { 0x1, 2 },
192 .offset = 0x2000,
211 .l = 0x14,
212 .alpha = 0x0,
213 .config_ctl_val = 0x20485699,
214 .config_ctl_hi_val = 0x00002067,
215 .test_ctl_val = 0x40000000,
216 .test_ctl_hi_val = 0x00000002,
217 .user_ctl_val = 0x00000001,
218 .user_ctl_hi_val = 0x00014805,
222 .offset = 0x3000,
239 { P_BI_TCXO, 0 },
249 { P_BI_TCXO, 0 },
263 { P_BI_TCXO, 0 },
275 { P_BI_TCXO, 0 },
285 { P_BI_TCXO, 0 },
297 { P_BI_TCXO, 0 },
311 { P_BI_TCXO, 0 },
323 { P_BI_TCXO, 0 },
337 { P_BI_TCXO, 0 },
349 { P_BI_TCXO, 0 },
359 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
360 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
361 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
362 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
363 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
368 .cmd_rcgr = 0x6010,
369 .mnd_width = 0,
382 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
383 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
384 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
389 .cmd_rcgr = 0xf004,
403 .cmd_rcgr = 0x10004,
417 F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
418 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
419 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
420 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
425 .cmd_rcgr = 0x9064,
426 .mnd_width = 0,
439 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0),
444 .cmd_rcgr = 0x5004,
445 .mnd_width = 0,
458 .cmd_rcgr = 0x5028,
459 .mnd_width = 0,
472 .cmd_rcgr = 0x504c,
473 .mnd_width = 0,
486 .cmd_rcgr = 0x5070,
487 .mnd_width = 0,
500 F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0),
501 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
502 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
503 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
508 .cmd_rcgr = 0x603c,
509 .mnd_width = 0,
522 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
523 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
524 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
525 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
530 .cmd_rcgr = 0xe014,
531 .mnd_width = 0,
544 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
545 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
546 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
547 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
548 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
553 .cmd_rcgr = 0x9010,
554 .mnd_width = 0,
568 .cmd_rcgr = 0x903c,
569 .mnd_width = 0,
582 .cmd_rcgr = 0xa010,
583 .mnd_width = 0,
597 .cmd_rcgr = 0xa034,
598 .mnd_width = 0,
611 .cmd_rcgr = 0xb00c,
612 .mnd_width = 0,
625 .cmd_rcgr = 0xb030,
626 .mnd_width = 0,
639 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
640 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
641 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
642 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
647 .cmd_rcgr = 0xc004,
648 .mnd_width = 0,
661 .cmd_rcgr = 0xc024,
662 .mnd_width = 0,
675 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
676 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
677 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
678 F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0),
679 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
684 .cmd_rcgr = 0x7010,
685 .mnd_width = 0,
699 F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0),
700 F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0),
701 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
702 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
703 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
704 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
709 .cmd_rcgr = 0xd004,
710 .mnd_width = 0,
723 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
724 F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0),
725 F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0),
726 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
731 .cmd_rcgr = 0x11004,
732 .mnd_width = 0,
747 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
752 .cmd_rcgr = 0x4004,
766 .cmd_rcgr = 0x4024,
780 .cmd_rcgr = 0x4044,
794 .cmd_rcgr = 0x4064,
808 .cmd_rcgr = 0x4084,
822 F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0),
827 .cmd_rcgr = 0x6058,
828 .mnd_width = 0,
841 .halt_reg = 0x6070,
844 .enable_reg = 0x6070,
845 .enable_mask = BIT(0),
859 .halt_reg = 0x6054,
862 .enable_reg = 0x6054,
863 .enable_mask = BIT(0),
877 .halt_reg = 0x6038,
880 .enable_reg = 0x6038,
881 .enable_mask = BIT(0),
890 .halt_reg = 0x6028,
893 .enable_reg = 0x6028,
894 .enable_mask = BIT(0),
908 .halt_reg = 0x13004,
911 .enable_reg = 0x13004,
912 .enable_mask = BIT(0),
921 .halt_reg = 0xf01c,
924 .enable_reg = 0xf01c,
925 .enable_mask = BIT(0),
939 .halt_reg = 0x1001c,
942 .enable_reg = 0x1001c,
943 .enable_mask = BIT(0),
957 .halt_reg = 0x14010,
960 .enable_reg = 0x14010,
961 .enable_mask = BIT(0),
975 .halt_reg = 0x12004,
978 .enable_reg = 0x12004,
979 .enable_mask = BIT(0),
993 .halt_reg = 0x501c,
996 .enable_reg = 0x501c,
997 .enable_mask = BIT(0),
1011 .halt_reg = 0x5040,
1014 .enable_reg = 0x5040,
1015 .enable_mask = BIT(0),
1029 .halt_reg = 0x5064,
1032 .enable_reg = 0x5064,
1033 .enable_mask = BIT(0),
1047 .halt_reg = 0x5088,
1050 .enable_reg = 0x5088,
1051 .enable_mask = BIT(0),
1065 .halt_reg = 0x5020,
1068 .enable_reg = 0x5020,
1069 .enable_mask = BIT(0),
1083 .halt_reg = 0x5044,
1086 .enable_reg = 0x5044,
1087 .enable_mask = BIT(0),
1101 .halt_reg = 0x5068,
1104 .enable_reg = 0x5068,
1105 .enable_mask = BIT(0),
1119 .halt_reg = 0x508c,
1122 .enable_reg = 0x508c,
1123 .enable_mask = BIT(0),
1137 .halt_reg = 0xe02c,
1140 .enable_reg = 0xe02c,
1141 .enable_mask = BIT(0),
1155 .halt_reg = 0xe00c,
1158 .enable_reg = 0xe00c,
1159 .enable_mask = BIT(0),
1168 .halt_reg = 0x9080,
1171 .enable_reg = 0x9080,
1172 .enable_mask = BIT(0),
1181 .halt_reg = 0x9028,
1184 .enable_reg = 0x9028,
1185 .enable_mask = BIT(0),
1199 .halt_reg = 0x907c,
1202 .enable_reg = 0x907c,
1203 .enable_mask = BIT(0),
1217 .halt_reg = 0x9054,
1220 .enable_reg = 0x9054,
1221 .enable_mask = BIT(0),
1235 .halt_reg = 0x9038,
1238 .enable_reg = 0x9038,
1239 .enable_mask = BIT(0),
1253 .halt_reg = 0xa058,
1256 .enable_reg = 0xa058,
1257 .enable_mask = BIT(0),
1266 .halt_reg = 0xa028,
1269 .enable_reg = 0xa028,
1270 .enable_mask = BIT(0),
1284 .halt_reg = 0xa054,
1287 .enable_reg = 0xa054,
1288 .enable_mask = BIT(0),
1302 .halt_reg = 0xa04c,
1305 .enable_reg = 0xa04c,
1306 .enable_mask = BIT(0),
1320 .halt_reg = 0xa030,
1323 .enable_reg = 0xa030,
1324 .enable_mask = BIT(0),
1338 .halt_reg = 0xb054,
1341 .enable_reg = 0xb054,
1342 .enable_mask = BIT(0),
1351 .halt_reg = 0xb024,
1354 .enable_reg = 0xb024,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0xb050,
1372 .enable_reg = 0xb050,
1373 .enable_mask = BIT(0),
1387 .halt_reg = 0xb048,
1390 .enable_reg = 0xb048,
1391 .enable_mask = BIT(0),
1405 .halt_reg = 0xb02c,
1408 .enable_reg = 0xb02c,
1409 .enable_mask = BIT(0),
1423 .halt_reg = 0xc01c,
1426 .enable_reg = 0xc01c,
1427 .enable_mask = BIT(0),
1441 .halt_reg = 0xc044,
1444 .enable_reg = 0xc044,
1445 .enable_mask = BIT(0),
1459 .halt_reg = 0xc03c,
1462 .enable_reg = 0xc03c,
1463 .enable_mask = BIT(0),
1477 .halt_reg = 0x7040,
1480 .enable_reg = 0x7040,
1481 .enable_mask = BIT(0),
1495 .halt_reg = 0x703c,
1498 .enable_reg = 0x703c,
1499 .enable_mask = BIT(0),
1513 .halt_reg = 0x7038,
1516 .enable_reg = 0x7038,
1517 .enable_mask = BIT(0),
1526 .halt_reg = 0x7028,
1529 .enable_reg = 0x7028,
1530 .enable_mask = BIT(0),
1544 .halt_reg = 0xd01c,
1547 .enable_reg = 0xd01c,
1548 .enable_mask = BIT(0),
1562 .halt_reg = 0x1101c,
1565 .enable_reg = 0x1101c,
1566 .enable_mask = BIT(0),
1580 .halt_reg = 0x401c,
1583 .enable_reg = 0x401c,
1584 .enable_mask = BIT(0),
1598 .halt_reg = 0x403c,
1601 .enable_reg = 0x403c,
1602 .enable_mask = BIT(0),
1616 .halt_reg = 0x405c,
1619 .enable_reg = 0x405c,
1620 .enable_mask = BIT(0),
1634 .halt_reg = 0x407c,
1637 .enable_reg = 0x407c,
1638 .enable_mask = BIT(0),
1652 .halt_reg = 0x409c,
1655 .enable_reg = 0x409c,
1656 .enable_mask = BIT(0),
1670 .halt_reg = 0x1400c,
1673 .enable_reg = 0x1400c,
1674 .enable_mask = BIT(0),
1683 .halt_reg = 0xe034,
1686 .enable_reg = 0xe034,
1687 .enable_mask = BIT(0),
1696 .gdscr = 0x6004,
1705 .gdscr = 0x7004,
1714 .gdscr = 0x9004,
1722 .gdscr = 0xa004,
1730 .gdscr = 0xb004,
1738 .gdscr = 0x14004,
1849 .max_register = 0x16000,