Lines Matching +full:0 +full:x9038
29 .offset = 0x0,
44 { 0x0, 1 },
45 { 0x1, 2 },
50 .offset = 0x0,
67 .offset = 0x1000,
82 .offset = 0x1000,
99 .offset = 0x2000,
114 .offset = 0x2000,
131 .offset = 0x3000,
146 .offset = 0x3000,
163 { P_BI_TCXO, 0 },
179 F(19200000, P_BI_TCXO, 1, 0, 0),
180 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
181 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
182 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
183 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
184 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
198 .cmd_rcgr = 0x600c,
199 .mnd_width = 0,
213 F(19200000, P_BI_TCXO, 1, 0, 0),
214 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
215 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
216 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
221 .cmd_rcgr = 0xb0d8,
235 F(19200000, P_BI_TCXO, 1, 0, 0),
236 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
241 .cmd_rcgr = 0x9060,
242 .mnd_width = 0,
255 F(19200000, P_BI_TCXO, 1, 0, 0),
256 F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0),
257 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
262 .cmd_rcgr = 0x5004,
263 .mnd_width = 0,
277 .cmd_rcgr = 0x5028,
278 .mnd_width = 0,
292 .cmd_rcgr = 0x504c,
293 .mnd_width = 0,
307 .cmd_rcgr = 0x5070,
308 .mnd_width = 0,
322 F(19200000, P_BI_TCXO, 1, 0, 0),
323 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
324 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
325 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
326 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
327 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
332 .cmd_rcgr = 0x6038,
333 .mnd_width = 0,
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
348 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
349 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
350 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
355 .cmd_rcgr = 0xb0b0,
356 .mnd_width = 0,
369 F(19200000, P_BI_TCXO, 1, 0, 0),
370 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
371 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
372 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
373 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
378 .cmd_rcgr = 0xb088,
379 .mnd_width = 0,
392 F(19200000, P_BI_TCXO, 1, 0, 0),
393 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
394 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
395 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
396 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
397 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
402 .cmd_rcgr = 0x900c,
403 .mnd_width = 0,
417 F(19200000, P_BI_TCXO, 1, 0, 0),
418 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
419 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
420 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
425 .cmd_rcgr = 0x9038,
426 .mnd_width = 0,
439 .cmd_rcgr = 0xa00c,
440 .mnd_width = 0,
454 .cmd_rcgr = 0xa030,
455 .mnd_width = 0,
468 .cmd_rcgr = 0xb004,
469 .mnd_width = 0,
483 .cmd_rcgr = 0xb024,
484 .mnd_width = 0,
497 F(19200000, P_BI_TCXO, 1, 0, 0),
498 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
499 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
500 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
501 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
502 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
503 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
508 .cmd_rcgr = 0x700c,
509 .mnd_width = 0,
523 .cmd_rcgr = 0x800c,
524 .mnd_width = 0,
538 .cmd_rcgr = 0xb04c,
539 .mnd_width = 0,
553 F(19200000, P_BI_TCXO, 1, 0, 0),
554 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
555 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
556 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
557 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
558 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
563 .cmd_rcgr = 0xb0f8,
564 .mnd_width = 0,
578 F(19200000, P_BI_TCXO, 1, 0, 0),
581 F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0),
586 .cmd_rcgr = 0x4004,
601 .cmd_rcgr = 0x4024,
616 .cmd_rcgr = 0x4044,
631 .cmd_rcgr = 0x4064,
646 F(19200000, P_BI_TCXO, 1, 0, 0),
647 F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0),
648 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
649 F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0),
650 F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0),
655 .cmd_rcgr = 0x6054,
656 .mnd_width = 0,
670 .halt_reg = 0x606c,
673 .enable_reg = 0x606c,
674 .enable_mask = BIT(0),
688 .halt_reg = 0x6050,
691 .enable_reg = 0x6050,
692 .enable_mask = BIT(0),
706 .halt_reg = 0x6034,
709 .enable_reg = 0x6034,
710 .enable_mask = BIT(0),
719 .halt_reg = 0x6024,
722 .enable_reg = 0x6024,
723 .enable_mask = BIT(0),
737 .halt_reg = 0xb12c,
740 .enable_reg = 0xb12c,
741 .enable_mask = BIT(0),
750 .halt_reg = 0xb124,
753 .enable_reg = 0xb124,
754 .enable_mask = BIT(0),
763 .halt_reg = 0xb0f0,
766 .enable_reg = 0xb0f0,
767 .enable_mask = BIT(0),
781 .halt_reg = 0xb11c,
784 .enable_reg = 0xb11c,
785 .enable_mask = BIT(0),
799 .halt_reg = 0x501c,
802 .enable_reg = 0x501c,
803 .enable_mask = BIT(0),
817 .halt_reg = 0x5040,
820 .enable_reg = 0x5040,
821 .enable_mask = BIT(0),
835 .halt_reg = 0x5064,
838 .enable_reg = 0x5064,
839 .enable_mask = BIT(0),
853 .halt_reg = 0x5088,
856 .enable_reg = 0x5088,
857 .enable_mask = BIT(0),
871 .halt_reg = 0x5020,
874 .enable_reg = 0x5020,
875 .enable_mask = BIT(0),
889 .halt_reg = 0x5044,
892 .enable_reg = 0x5044,
893 .enable_mask = BIT(0),
907 .halt_reg = 0x5068,
910 .enable_reg = 0x5068,
911 .enable_mask = BIT(0),
925 .halt_reg = 0x508c,
928 .enable_reg = 0x508c,
929 .enable_mask = BIT(0),
943 .halt_reg = 0xb0c8,
946 .enable_reg = 0xb0c8,
947 .enable_mask = BIT(0),
961 .halt_reg = 0xb0d0,
964 .enable_reg = 0xb0d0,
965 .enable_mask = BIT(0),
978 .halt_reg = 0xb084,
981 .enable_reg = 0xb084,
982 .enable_mask = BIT(0),
991 .halt_reg = 0xb078,
994 .enable_reg = 0xb078,
995 .enable_mask = BIT(0),
1004 .halt_reg = 0xb0a0,
1007 .enable_reg = 0xb0a0,
1008 .enable_mask = BIT(0),
1022 .halt_reg = 0xb07c,
1025 .enable_reg = 0xb07c,
1026 .enable_mask = BIT(0),
1035 .halt_reg = 0xb080,
1038 .enable_reg = 0xb080,
1039 .enable_mask = BIT(0),
1048 .halt_reg = 0x907c,
1051 .enable_reg = 0x907c,
1052 .enable_mask = BIT(0),
1061 .halt_reg = 0x9024,
1064 .enable_reg = 0x9024,
1065 .enable_mask = BIT(0),
1079 .halt_reg = 0x9078,
1082 .enable_reg = 0x9078,
1083 .enable_mask = BIT(0),
1097 .halt_reg = 0x9050,
1100 .enable_reg = 0x9050,
1101 .enable_mask = BIT(0),
1115 .halt_reg = 0x9034,
1118 .enable_reg = 0x9034,
1119 .enable_mask = BIT(0),
1132 .halt_reg = 0xa054,
1135 .enable_reg = 0xa054,
1136 .enable_mask = BIT(0),
1145 .halt_reg = 0xa024,
1148 .enable_reg = 0xa024,
1149 .enable_mask = BIT(0),
1163 .halt_reg = 0xa050,
1166 .enable_reg = 0xa050,
1167 .enable_mask = BIT(0),
1181 .halt_reg = 0xa048,
1184 .enable_reg = 0xa048,
1185 .enable_mask = BIT(0),
1199 .halt_reg = 0xa02c,
1202 .enable_reg = 0xa02c,
1203 .enable_mask = BIT(0),
1216 .halt_reg = 0xb01c,
1219 .enable_reg = 0xb01c,
1220 .enable_mask = BIT(0),
1234 .halt_reg = 0xb044,
1237 .enable_reg = 0xb044,
1238 .enable_mask = BIT(0),
1252 .halt_reg = 0xb03c,
1255 .enable_reg = 0xb03c,
1256 .enable_mask = BIT(0),
1270 .halt_reg = 0x703c,
1273 .enable_reg = 0x703c,
1274 .enable_mask = BIT(0),
1288 .halt_reg = 0x7038,
1291 .enable_reg = 0x7038,
1292 .enable_mask = BIT(0),
1306 .halt_reg = 0x7034,
1309 .enable_reg = 0x7034,
1310 .enable_mask = BIT(0),
1319 .halt_reg = 0x7024,
1322 .enable_reg = 0x7024,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0x803c,
1340 .enable_reg = 0x803c,
1341 .enable_mask = BIT(0),
1355 .halt_reg = 0x8038,
1358 .enable_reg = 0x8038,
1359 .enable_mask = BIT(0),
1373 .halt_reg = 0x8034,
1376 .enable_reg = 0x8034,
1377 .enable_mask = BIT(0),
1386 .halt_reg = 0x8024,
1389 .enable_reg = 0x8024,
1390 .enable_mask = BIT(0),
1404 .halt_reg = 0xb064,
1407 .enable_reg = 0xb064,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0xb110,
1425 .enable_reg = 0xb110,
1426 .enable_mask = BIT(0),
1440 .halt_reg = 0x401c,
1443 .enable_reg = 0x401c,
1444 .enable_mask = BIT(0),
1458 .halt_reg = 0x403c,
1461 .enable_reg = 0x403c,
1462 .enable_mask = BIT(0),
1476 .halt_reg = 0x405c,
1479 .enable_reg = 0x405c,
1480 .enable_mask = BIT(0),
1494 .halt_reg = 0x407c,
1497 .enable_reg = 0x407c,
1498 .enable_mask = BIT(0),
1512 .halt_reg = 0xb13c,
1515 .enable_reg = 0xb13c,
1516 .enable_mask = BIT(0),
1525 .halt_reg = 0xb0a8,
1528 .enable_reg = 0xb0a8,
1529 .enable_mask = BIT(0),
1540 .gdscr = 0x6004,
1549 .gdscr = 0x7004,
1558 .gdscr = 0x8004,
1567 .gdscr = 0x9004,
1577 .gdscr = 0xa004,
1587 .gdscr = 0xb134,
1696 .max_register = 0xd004,
1723 cam_cc_pll_config.l = 0x1f; in cam_cc_sdm845_probe()
1724 cam_cc_pll_config.alpha = 0x4000; in cam_cc_sdm845_probe()
1727 cam_cc_pll_config.l = 0x2a; in cam_cc_sdm845_probe()
1728 cam_cc_pll_config.alpha = 0x1556; in cam_cc_sdm845_probe()
1731 cam_cc_pll_config.l = 0x32; in cam_cc_sdm845_probe()
1732 cam_cc_pll_config.alpha = 0x0; in cam_cc_sdm845_probe()
1735 cam_cc_pll_config.l = 0x14; in cam_cc_sdm845_probe()