439 static int ma35d1_get_pll_setting(struct device_node *clk_node, u32 *pllmode)  in ma35d1_get_pll_setting()  argument
448 			pllmode[i] = PLL_MODE_INT;  in ma35d1_get_pll_setting()
450 			pllmode[i] = PLL_MODE_FRAC;  in ma35d1_get_pll_setting()
452 			pllmode[i] = PLL_MODE_SS;  in ma35d1_get_pll_setting()
466 	u32 pllmode[PLL_MAX_NUM];  in ma35d1_clocks_probe()  local
482 	ret = ma35d1_get_pll_setting(clk_node, pllmode);  in ma35d1_clocks_probe()
501 	hws[CAPLL] = ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll",  in ma35d1_clocks_probe()
504 	hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll",  in ma35d1_clocks_probe()
506 	hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll",  in ma35d1_clocks_probe()
508 	hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll",  in ma35d1_clocks_probe()
510 	hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll",  in ma35d1_clocks_probe()