Lines Matching refs:REG_CLK_SYSCLK0
23 #define REG_CLK_SYSCLK0 0x04 macro
552 clk_base + REG_CLK_SYSCLK0, 4); in ma35d1_clocks_probe()
554 clk_base + REG_CLK_SYSCLK0, 5); in ma35d1_clocks_probe()
562 clk_base + REG_CLK_SYSCLK0, 8); in ma35d1_clocks_probe()
569 clk_base + REG_CLK_SYSCLK0, 9); in ma35d1_clocks_probe()
576 clk_base + REG_CLK_SYSCLK0, 10); in ma35d1_clocks_probe()
583 clk_base + REG_CLK_SYSCLK0, 11); in ma35d1_clocks_probe()
588 clk_base + REG_CLK_SYSCLK0, 16); in ma35d1_clocks_probe()
592 clk_base + REG_CLK_SYSCLK0, 17); in ma35d1_clocks_probe()
595 clk_base + REG_CLK_SYSCLK0, 18); in ma35d1_clocks_probe()
598 clk_base + REG_CLK_SYSCLK0, 19); in ma35d1_clocks_probe()
600 clk_base + REG_CLK_SYSCLK0, 20); in ma35d1_clocks_probe()
602 clk_base + REG_CLK_SYSCLK0, 21); in ma35d1_clocks_probe()
604 clk_base + REG_CLK_SYSCLK0, 22); in ma35d1_clocks_probe()
609 clk_base + REG_CLK_SYSCLK0, 24); in ma35d1_clocks_probe()
611 clk_base + REG_CLK_SYSCLK0, 25); in ma35d1_clocks_probe()
615 clk_base + REG_CLK_SYSCLK0, 26); in ma35d1_clocks_probe()
621 clk_base + REG_CLK_SYSCLK0, 27); in ma35d1_clocks_probe()
623 clk_base + REG_CLK_SYSCLK0, 28); in ma35d1_clocks_probe()
630 clk_base + REG_CLK_SYSCLK0, 29); in ma35d1_clocks_probe()
637 clk_base + REG_CLK_SYSCLK0, 30); in ma35d1_clocks_probe()