Lines Matching refs:REG_CLK_CLKSEL0

28 #define REG_CLK_CLKSEL0		0x18  macro
518 						 clk_base + REG_CLK_CLKSEL0, 0, 2,  in ma35d1_clocks_probe()
527 	hws[SYSCLK0_MUX] = ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
530 	hws[SYSCLK1_MUX] = ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
585 	hws[SDH0_MUX] = ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
589 	hws[SDH1_MUX] = ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
606 	hws[GFX_MUX] = ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
612 	hws[DCU_MUX] = ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
625 	hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
631 	hws[CCAP1_MUX] = ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()
670 	hws[DBG_MUX] = ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL0,  in ma35d1_clocks_probe()