Lines Matching refs:dev
377 static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char *name, in ma35d1_clk_mux_parent() argument
382 return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, in ma35d1_clk_mux_parent()
387 static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, in ma35d1_clk_mux() argument
392 return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, in ma35d1_clk_mux()
397 static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *name, in ma35d1_clk_divider() argument
401 return devm_clk_hw_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, in ma35d1_clk_divider()
405 static struct clk_hw *ma35d1_clk_divider_pow2(struct device *dev, const char *name, in ma35d1_clk_divider_pow2() argument
409 return devm_clk_hw_register_divider(dev, name, parent, in ma35d1_clk_divider_pow2()
414 static struct clk_hw *ma35d1_clk_divider_table(struct device *dev, const char *name, in ma35d1_clk_divider_table() argument
419 return devm_clk_hw_register_divider_table(dev, name, parent, 0, in ma35d1_clk_divider_table()
424 static struct clk_hw *ma35d1_clk_fixed_factor(struct device *dev, const char *name, in ma35d1_clk_fixed_factor() argument
428 return devm_clk_hw_register_fixed_factor(dev, name, parent, in ma35d1_clk_fixed_factor()
432 static struct clk_hw *ma35d1_clk_gate(struct device *dev, const char *name, const char *parent, in ma35d1_clk_gate() argument
435 return devm_clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, in ma35d1_clk_gate()
461 struct device *dev = &pdev->dev; in ma35d1_clocks_probe() local
462 struct device_node *clk_node = pdev->dev.of_node; in ma35d1_clocks_probe()
469 ma35d1_hw_data = devm_kzalloc(dev, in ma35d1_clocks_probe()
484 dev_err(dev, "Invalid PLL setting!\n"); in ma35d1_clocks_probe()
489 hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt", in ma35d1_clocks_probe()
492 hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt", in ma35d1_clocks_probe()
495 hws[HIRC_GATE] = ma35d1_clk_gate(dev, "hirc_gate", "hirc", in ma35d1_clocks_probe()
498 hws[LIRC_GATE] = ma35d1_clk_gate(dev, "lirc_gate", "lirc", in ma35d1_clocks_probe()
501 hws[CAPLL] = ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", in ma35d1_clocks_probe()
504 hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", in ma35d1_clocks_probe()
506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
508 hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", in ma35d1_clocks_probe()
510 hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", in ma35d1_clocks_probe()
513 hws[EPLL_DIV2] = ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2); in ma35d1_clocks_probe()
514 hws[EPLL_DIV4] = ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4); in ma35d1_clocks_probe()
515 hws[EPLL_DIV8] = ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8); in ma35d1_clocks_probe()
517 hws[CA35CLK_MUX] = ma35d1_clk_mux_parent(dev, "ca35clk_mux", in ma35d1_clocks_probe()
521 hws[AXICLK_DIV2] = ma35d1_clk_fixed_factor(dev, "capll_div2", "ca35clk_mux", 1, 2); in ma35d1_clocks_probe()
522 hws[AXICLK_DIV4] = ma35d1_clk_fixed_factor(dev, "capll_div4", "ca35clk_mux", 1, 4); in ma35d1_clocks_probe()
524 hws[AXICLK_MUX] = ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
527 hws[SYSCLK0_MUX] = ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
530 hws[SYSCLK1_MUX] = ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
533 hws[SYSCLK1_DIV2] = ma35d1_clk_fixed_factor(dev, "sysclk1_div2", "sysclk1_mux", 1, 2); in ma35d1_clocks_probe()
536 hws[HCLK0] = ma35d1_clk_fixed_factor(dev, "hclk0", "sysclk1_mux", 1, 1); in ma35d1_clocks_probe()
537 hws[HCLK1] = ma35d1_clk_fixed_factor(dev, "hclk1", "sysclk1_mux", 1, 1); in ma35d1_clocks_probe()
538 hws[HCLK2] = ma35d1_clk_fixed_factor(dev, "hclk2", "sysclk1_mux", 1, 1); in ma35d1_clocks_probe()
539 hws[PCLK0] = ma35d1_clk_fixed_factor(dev, "pclk0", "sysclk1_mux", 1, 1); in ma35d1_clocks_probe()
540 hws[PCLK1] = ma35d1_clk_fixed_factor(dev, "pclk1", "sysclk1_mux", 1, 1); in ma35d1_clocks_probe()
541 hws[PCLK2] = ma35d1_clk_fixed_factor(dev, "pclk2", "sysclk1_mux", 1, 1); in ma35d1_clocks_probe()
543 hws[HCLK3] = ma35d1_clk_fixed_factor(dev, "hclk3", "sysclk1_mux", 1, 2); in ma35d1_clocks_probe()
544 hws[PCLK3] = ma35d1_clk_fixed_factor(dev, "pclk3", "sysclk1_mux", 1, 2); in ma35d1_clocks_probe()
545 hws[PCLK4] = ma35d1_clk_fixed_factor(dev, "pclk4", "sysclk1_mux", 1, 2); in ma35d1_clocks_probe()
551 hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", in ma35d1_clocks_probe()
553 hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", in ma35d1_clocks_probe()
556 hws[CAN0_MUX] = ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
558 hws[CAN0_DIV] = ma35d1_clk_divider_table(dev, "can0_div", "can0_mux", in ma35d1_clocks_probe()
561 hws[CAN0_GATE] = ma35d1_clk_gate(dev, "can0_gate", "can0_div", in ma35d1_clocks_probe()
563 hws[CAN1_MUX] = ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
565 hws[CAN1_DIV] = ma35d1_clk_divider_table(dev, "can1_div", "can1_mux", in ma35d1_clocks_probe()
568 hws[CAN1_GATE] = ma35d1_clk_gate(dev, "can1_gate", "can1_div", in ma35d1_clocks_probe()
570 hws[CAN2_MUX] = ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
572 hws[CAN2_DIV] = ma35d1_clk_divider_table(dev, "can2_div", "can2_mux", in ma35d1_clocks_probe()
575 hws[CAN2_GATE] = ma35d1_clk_gate(dev, "can2_gate", "can2_div", in ma35d1_clocks_probe()
577 hws[CAN3_MUX] = ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
579 hws[CAN3_DIV] = ma35d1_clk_divider_table(dev, "can3_div", "can3_mux", in ma35d1_clocks_probe()
582 hws[CAN3_GATE] = ma35d1_clk_gate(dev, "can3_gate", "can3_div", in ma35d1_clocks_probe()
585 hws[SDH0_MUX] = ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
587 hws[SDH0_GATE] = ma35d1_clk_gate(dev, "sdh0_gate", "sdh0_mux", in ma35d1_clocks_probe()
589 hws[SDH1_MUX] = ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
591 hws[SDH1_GATE] = ma35d1_clk_gate(dev, "sdh1_gate", "sdh1_mux", in ma35d1_clocks_probe()
594 hws[NAND_GATE] = ma35d1_clk_gate(dev, "nand_gate", "hclk1", in ma35d1_clocks_probe()
597 hws[USBD_GATE] = ma35d1_clk_gate(dev, "usbd_gate", "usbphy0", in ma35d1_clocks_probe()
599 hws[USBH_GATE] = ma35d1_clk_gate(dev, "usbh_gate", "usbphy0", in ma35d1_clocks_probe()
601 hws[HUSBH0_GATE] = ma35d1_clk_gate(dev, "husbh0_gate", "usbphy0", in ma35d1_clocks_probe()
603 hws[HUSBH1_GATE] = ma35d1_clk_gate(dev, "husbh1_gate", "usbphy0", in ma35d1_clocks_probe()
606 hws[GFX_MUX] = ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
608 hws[GFX_GATE] = ma35d1_clk_gate(dev, "gfx_gate", "gfx_mux", in ma35d1_clocks_probe()
610 hws[VC8K_GATE] = ma35d1_clk_gate(dev, "vc8k_gate", "sysclk0_mux", in ma35d1_clocks_probe()
612 hws[DCU_MUX] = ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
614 hws[DCU_GATE] = ma35d1_clk_gate(dev, "dcu_gate", "dcu_mux", in ma35d1_clocks_probe()
616 hws[DCUP_DIV] = ma35d1_clk_divider_table(dev, "dcup_div", "vpll", in ma35d1_clocks_probe()
620 hws[EMAC0_GATE] = ma35d1_clk_gate(dev, "emac0_gate", "epll_div2", in ma35d1_clocks_probe()
622 hws[EMAC1_GATE] = ma35d1_clk_gate(dev, "emac1_gate", "epll_div2", in ma35d1_clocks_probe()
625 hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
627 hws[CCAP0_DIV] = ma35d1_clk_divider(dev, "ccap0_div", "ccap0_mux", in ma35d1_clocks_probe()
629 hws[CCAP0_GATE] = ma35d1_clk_gate(dev, "ccap0_gate", "ccap0_div", in ma35d1_clocks_probe()
631 hws[CCAP1_MUX] = ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
633 hws[CCAP1_DIV] = ma35d1_clk_divider(dev, "ccap1_div", "ccap1_mux", in ma35d1_clocks_probe()
636 hws[CCAP1_GATE] = ma35d1_clk_gate(dev, "ccap1_gate", "ccap1_div", in ma35d1_clocks_probe()
639 hws[PDMA0_GATE] = ma35d1_clk_gate(dev, "pdma0_gate", "hclk0", in ma35d1_clocks_probe()
641 hws[PDMA1_GATE] = ma35d1_clk_gate(dev, "pdma1_gate", "hclk0", in ma35d1_clocks_probe()
643 hws[PDMA2_GATE] = ma35d1_clk_gate(dev, "pdma2_gate", "hclk0", in ma35d1_clocks_probe()
645 hws[PDMA3_GATE] = ma35d1_clk_gate(dev, "pdma3_gate", "hclk0", in ma35d1_clocks_probe()
648 hws[WH0_GATE] = ma35d1_clk_gate(dev, "wh0_gate", "hclk0", in ma35d1_clocks_probe()
650 hws[WH1_GATE] = ma35d1_clk_gate(dev, "wh1_gate", "hclk0", in ma35d1_clocks_probe()
653 hws[HWS_GATE] = ma35d1_clk_gate(dev, "hws_gate", "hclk0", in ma35d1_clocks_probe()
656 hws[EBI_GATE] = ma35d1_clk_gate(dev, "ebi_gate", "hclk0", in ma35d1_clocks_probe()
659 hws[SRAM0_GATE] = ma35d1_clk_gate(dev, "sram0_gate", "hclk0", in ma35d1_clocks_probe()
661 hws[SRAM1_GATE] = ma35d1_clk_gate(dev, "sram1_gate", "hclk0", in ma35d1_clocks_probe()
664 hws[ROM_GATE] = ma35d1_clk_gate(dev, "rom_gate", "hclk0", in ma35d1_clocks_probe()
667 hws[TRA_GATE] = ma35d1_clk_gate(dev, "tra_gate", "hclk0", in ma35d1_clocks_probe()
670 hws[DBG_MUX] = ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
672 hws[DBG_GATE] = ma35d1_clk_gate(dev, "dbg_gate", "hclk0", in ma35d1_clocks_probe()
675 hws[CKO_MUX] = ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
677 hws[CKO_DIV] = ma35d1_clk_divider_pow2(dev, "cko_div", "cko_mux", in ma35d1_clocks_probe()
679 hws[CKO_GATE] = ma35d1_clk_gate(dev, "cko_gate", "cko_div", in ma35d1_clocks_probe()
682 hws[GTMR_GATE] = ma35d1_clk_gate(dev, "gtmr_gate", "hirc", in ma35d1_clocks_probe()
685 hws[GPA_GATE] = ma35d1_clk_gate(dev, "gpa_gate", "hclk0", in ma35d1_clocks_probe()
687 hws[GPB_GATE] = ma35d1_clk_gate(dev, "gpb_gate", "hclk0", in ma35d1_clocks_probe()
689 hws[GPC_GATE] = ma35d1_clk_gate(dev, "gpc_gate", "hclk0", in ma35d1_clocks_probe()
691 hws[GPD_GATE] = ma35d1_clk_gate(dev, "gpd_gate", "hclk0", in ma35d1_clocks_probe()
693 hws[GPE_GATE] = ma35d1_clk_gate(dev, "gpe_gate", "hclk0", in ma35d1_clocks_probe()
695 hws[GPF_GATE] = ma35d1_clk_gate(dev, "gpf_gate", "hclk0", in ma35d1_clocks_probe()
697 hws[GPG_GATE] = ma35d1_clk_gate(dev, "gpg_gate", "hclk0", in ma35d1_clocks_probe()
699 hws[GPH_GATE] = ma35d1_clk_gate(dev, "gph_gate", "hclk0", in ma35d1_clocks_probe()
701 hws[GPI_GATE] = ma35d1_clk_gate(dev, "gpi_gate", "hclk0", in ma35d1_clocks_probe()
703 hws[GPJ_GATE] = ma35d1_clk_gate(dev, "gpj_gate", "hclk0", in ma35d1_clocks_probe()
705 hws[GPK_GATE] = ma35d1_clk_gate(dev, "gpk_gate", "hclk0", in ma35d1_clocks_probe()
707 hws[GPL_GATE] = ma35d1_clk_gate(dev, "gpl_gate", "hclk0", in ma35d1_clocks_probe()
709 hws[GPM_GATE] = ma35d1_clk_gate(dev, "gpm_gate", "hclk0", in ma35d1_clocks_probe()
711 hws[GPN_GATE] = ma35d1_clk_gate(dev, "gpn_gate", "hclk0", in ma35d1_clocks_probe()
714 hws[TMR0_MUX] = ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
717 hws[TMR0_GATE] = ma35d1_clk_gate(dev, "tmr0_gate", "tmr0_mux", in ma35d1_clocks_probe()
719 hws[TMR1_MUX] = ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
722 hws[TMR1_GATE] = ma35d1_clk_gate(dev, "tmr1_gate", "tmr1_mux", in ma35d1_clocks_probe()
724 hws[TMR2_MUX] = ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
727 hws[TMR2_GATE] = ma35d1_clk_gate(dev, "tmr2_gate", "tmr2_mux", in ma35d1_clocks_probe()
729 hws[TMR3_MUX] = ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
732 hws[TMR3_GATE] = ma35d1_clk_gate(dev, "tmr3_gate", "tmr3_mux", in ma35d1_clocks_probe()
734 hws[TMR4_MUX] = ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
737 hws[TMR4_GATE] = ma35d1_clk_gate(dev, "tmr4_gate", "tmr4_mux", in ma35d1_clocks_probe()
739 hws[TMR5_MUX] = ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
742 hws[TMR5_GATE] = ma35d1_clk_gate(dev, "tmr5_gate", "tmr5_mux", in ma35d1_clocks_probe()
744 hws[TMR6_MUX] = ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
747 hws[TMR6_GATE] = ma35d1_clk_gate(dev, "tmr6_gate", "tmr6_mux", in ma35d1_clocks_probe()
749 hws[TMR7_MUX] = ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
752 hws[TMR7_GATE] = ma35d1_clk_gate(dev, "tmr7_gate", "tmr7_mux", in ma35d1_clocks_probe()
754 hws[TMR8_MUX] = ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
757 hws[TMR8_GATE] = ma35d1_clk_gate(dev, "tmr8_gate", "tmr8_mux", in ma35d1_clocks_probe()
759 hws[TMR9_MUX] = ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
762 hws[TMR9_GATE] = ma35d1_clk_gate(dev, "tmr9_gate", "tmr9_mux", in ma35d1_clocks_probe()
764 hws[TMR10_MUX] = ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
767 hws[TMR10_GATE] = ma35d1_clk_gate(dev, "tmr10_gate", "tmr10_mux", in ma35d1_clocks_probe()
769 hws[TMR11_MUX] = ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
772 hws[TMR11_GATE] = ma35d1_clk_gate(dev, "tmr11_gate", "tmr11_mux", in ma35d1_clocks_probe()
775 hws[UART0_MUX] = ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
777 hws[UART0_DIV] = ma35d1_clk_divider(dev, "uart0_div", "uart0_mux", in ma35d1_clocks_probe()
780 hws[UART0_GATE] = ma35d1_clk_gate(dev, "uart0_gate", "uart0_div", in ma35d1_clocks_probe()
782 hws[UART1_MUX] = ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
784 hws[UART1_DIV] = ma35d1_clk_divider(dev, "uart1_div", "uart1_mux", in ma35d1_clocks_probe()
787 hws[UART1_GATE] = ma35d1_clk_gate(dev, "uart1_gate", "uart1_div", in ma35d1_clocks_probe()
789 hws[UART2_MUX] = ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
791 hws[UART2_DIV] = ma35d1_clk_divider(dev, "uart2_div", "uart2_mux", in ma35d1_clocks_probe()
794 hws[UART2_GATE] = ma35d1_clk_gate(dev, "uart2_gate", "uart2_div", in ma35d1_clocks_probe()
796 hws[UART3_MUX] = ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
798 hws[UART3_DIV] = ma35d1_clk_divider(dev, "uart3_div", "uart3_mux", in ma35d1_clocks_probe()
801 hws[UART3_GATE] = ma35d1_clk_gate(dev, "uart3_gate", "uart3_div", in ma35d1_clocks_probe()
803 hws[UART4_MUX] = ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
805 hws[UART4_DIV] = ma35d1_clk_divider(dev, "uart4_div", "uart4_mux", in ma35d1_clocks_probe()
808 hws[UART4_GATE] = ma35d1_clk_gate(dev, "uart4_gate", "uart4_div", in ma35d1_clocks_probe()
810 hws[UART5_MUX] = ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
812 hws[UART5_DIV] = ma35d1_clk_divider(dev, "uart5_div", "uart5_mux", in ma35d1_clocks_probe()
815 hws[UART5_GATE] = ma35d1_clk_gate(dev, "uart5_gate", "uart5_div", in ma35d1_clocks_probe()
817 hws[UART6_MUX] = ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
819 hws[UART6_DIV] = ma35d1_clk_divider(dev, "uart6_div", "uart6_mux", in ma35d1_clocks_probe()
822 hws[UART6_GATE] = ma35d1_clk_gate(dev, "uart6_gate", "uart6_div", in ma35d1_clocks_probe()
824 hws[UART7_MUX] = ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
826 hws[UART7_DIV] = ma35d1_clk_divider(dev, "uart7_div", "uart7_mux", in ma35d1_clocks_probe()
829 hws[UART7_GATE] = ma35d1_clk_gate(dev, "uart7_gate", "uart7_div", in ma35d1_clocks_probe()
831 hws[UART8_MUX] = ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
833 hws[UART8_DIV] = ma35d1_clk_divider(dev, "uart8_div", "uart8_mux", in ma35d1_clocks_probe()
836 hws[UART8_GATE] = ma35d1_clk_gate(dev, "uart8_gate", "uart8_div", in ma35d1_clocks_probe()
838 hws[UART9_MUX] = ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
840 hws[UART9_DIV] = ma35d1_clk_divider(dev, "uart9_div", "uart9_mux", in ma35d1_clocks_probe()
843 hws[UART9_GATE] = ma35d1_clk_gate(dev, "uart9_gate", "uart9_div", in ma35d1_clocks_probe()
845 hws[UART10_MUX] = ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
847 hws[UART10_DIV] = ma35d1_clk_divider(dev, "uart10_div", "uart10_mux", in ma35d1_clocks_probe()
850 hws[UART10_GATE] = ma35d1_clk_gate(dev, "uart10_gate", "uart10_div", in ma35d1_clocks_probe()
852 hws[UART11_MUX] = ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
854 hws[UART11_DIV] = ma35d1_clk_divider(dev, "uart11_div", "uart11_mux", in ma35d1_clocks_probe()
857 hws[UART11_GATE] = ma35d1_clk_gate(dev, "uart11_gate", "uart11_div", in ma35d1_clocks_probe()
859 hws[UART12_MUX] = ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
861 hws[UART12_DIV] = ma35d1_clk_divider(dev, "uart12_div", "uart12_mux", in ma35d1_clocks_probe()
864 hws[UART12_GATE] = ma35d1_clk_gate(dev, "uart12_gate", "uart12_div", in ma35d1_clocks_probe()
866 hws[UART13_MUX] = ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
868 hws[UART13_DIV] = ma35d1_clk_divider(dev, "uart13_div", "uart13_mux", in ma35d1_clocks_probe()
871 hws[UART13_GATE] = ma35d1_clk_gate(dev, "uart13_gate", "uart13_div", in ma35d1_clocks_probe()
873 hws[UART14_MUX] = ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
875 hws[UART14_DIV] = ma35d1_clk_divider(dev, "uart14_div", "uart14_mux", in ma35d1_clocks_probe()
878 hws[UART14_GATE] = ma35d1_clk_gate(dev, "uart14_gate", "uart14_div", in ma35d1_clocks_probe()
880 hws[UART15_MUX] = ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
882 hws[UART15_DIV] = ma35d1_clk_divider(dev, "uart15_div", "uart15_mux", in ma35d1_clocks_probe()
885 hws[UART15_GATE] = ma35d1_clk_gate(dev, "uart15_gate", "uart15_div", in ma35d1_clocks_probe()
887 hws[UART16_MUX] = ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
889 hws[UART16_DIV] = ma35d1_clk_divider(dev, "uart16_div", "uart16_mux", in ma35d1_clocks_probe()
892 hws[UART16_GATE] = ma35d1_clk_gate(dev, "uart16_gate", "uart16_div", in ma35d1_clocks_probe()
895 hws[RTC_GATE] = ma35d1_clk_gate(dev, "rtc_gate", "lxt", in ma35d1_clocks_probe()
897 hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", in ma35d1_clocks_probe()
900 hws[KPI_MUX] = ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
902 hws[KPI_DIV] = ma35d1_clk_divider(dev, "kpi_div", "kpi_mux", in ma35d1_clocks_probe()
905 hws[KPI_GATE] = ma35d1_clk_gate(dev, "kpi_gate", "kpi_div", in ma35d1_clocks_probe()
908 hws[I2C0_GATE] = ma35d1_clk_gate(dev, "i2c0_gate", "pclk0", in ma35d1_clocks_probe()
910 hws[I2C1_GATE] = ma35d1_clk_gate(dev, "i2c1_gate", "pclk1", in ma35d1_clocks_probe()
912 hws[I2C2_GATE] = ma35d1_clk_gate(dev, "i2c2_gate", "pclk2", in ma35d1_clocks_probe()
914 hws[I2C3_GATE] = ma35d1_clk_gate(dev, "i2c3_gate", "pclk0", in ma35d1_clocks_probe()
916 hws[I2C4_GATE] = ma35d1_clk_gate(dev, "i2c4_gate", "pclk1", in ma35d1_clocks_probe()
918 hws[I2C5_GATE] = ma35d1_clk_gate(dev, "i2c5_gate", "pclk2", in ma35d1_clocks_probe()
921 hws[QSPI0_MUX] = ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
923 hws[QSPI0_GATE] = ma35d1_clk_gate(dev, "qspi0_gate", "qspi0_mux", in ma35d1_clocks_probe()
925 hws[QSPI1_MUX] = ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
927 hws[QSPI1_GATE] = ma35d1_clk_gate(dev, "qspi1_gate", "qspi1_mux", in ma35d1_clocks_probe()
930 hws[SMC0_MUX] = ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
932 hws[SMC0_DIV] = ma35d1_clk_divider(dev, "smc0_div", "smc0_mux", in ma35d1_clocks_probe()
935 hws[SMC0_GATE] = ma35d1_clk_gate(dev, "smc0_gate", "smc0_div", in ma35d1_clocks_probe()
937 hws[SMC1_MUX] = ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
939 hws[SMC1_DIV] = ma35d1_clk_divider(dev, "smc1_div", "smc1_mux", in ma35d1_clocks_probe()
942 hws[SMC1_GATE] = ma35d1_clk_gate(dev, "smc1_gate", "smc1_div", in ma35d1_clocks_probe()
945 hws[WDT0_MUX] = ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
947 hws[WDT0_GATE] = ma35d1_clk_gate(dev, "wdt0_gate", "wdt0_mux", in ma35d1_clocks_probe()
949 hws[WDT1_MUX] = ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
951 hws[WDT1_GATE] = ma35d1_clk_gate(dev, "wdt1_gate", "wdt1_mux", in ma35d1_clocks_probe()
953 hws[WDT2_MUX] = ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
955 hws[WDT2_GATE] = ma35d1_clk_gate(dev, "wdt2_gate", "wdt2_mux", in ma35d1_clocks_probe()
958 hws[WWDT0_MUX] = ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
960 hws[WWDT1_MUX] = ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
962 hws[WWDT2_MUX] = ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
965 hws[EPWM0_GATE] = ma35d1_clk_gate(dev, "epwm0_gate", "pclk1", in ma35d1_clocks_probe()
967 hws[EPWM1_GATE] = ma35d1_clk_gate(dev, "epwm1_gate", "pclk2", in ma35d1_clocks_probe()
969 hws[EPWM2_GATE] = ma35d1_clk_gate(dev, "epwm2_gate", "pclk1", in ma35d1_clocks_probe()
972 hws[I2S0_MUX] = ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
974 hws[I2S0_GATE] = ma35d1_clk_gate(dev, "i2s0_gate", "i2s0_mux", in ma35d1_clocks_probe()
976 hws[I2S1_MUX] = ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
978 hws[I2S1_GATE] = ma35d1_clk_gate(dev, "i2s1_gate", "i2s1_mux", in ma35d1_clocks_probe()
981 hws[SSMCC_GATE] = ma35d1_clk_gate(dev, "ssmcc_gate", "pclk3", in ma35d1_clocks_probe()
983 hws[SSPCC_GATE] = ma35d1_clk_gate(dev, "sspcc_gate", "pclk3", in ma35d1_clocks_probe()
986 hws[SPI0_MUX] = ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
988 hws[SPI0_GATE] = ma35d1_clk_gate(dev, "spi0_gate", "spi0_mux", in ma35d1_clocks_probe()
990 hws[SPI1_MUX] = ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
992 hws[SPI1_GATE] = ma35d1_clk_gate(dev, "spi1_gate", "spi1_mux", in ma35d1_clocks_probe()
994 hws[SPI2_MUX] = ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
996 hws[SPI2_GATE] = ma35d1_clk_gate(dev, "spi2_gate", "spi2_mux", in ma35d1_clocks_probe()
998 hws[SPI3_MUX] = ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
1000 hws[SPI3_GATE] = ma35d1_clk_gate(dev, "spi3_gate", "spi3_mux", in ma35d1_clocks_probe()
1003 hws[ECAP0_GATE] = ma35d1_clk_gate(dev, "ecap0_gate", "pclk1", in ma35d1_clocks_probe()
1005 hws[ECAP1_GATE] = ma35d1_clk_gate(dev, "ecap1_gate", "pclk2", in ma35d1_clocks_probe()
1007 hws[ECAP2_GATE] = ma35d1_clk_gate(dev, "ecap2_gate", "pclk1", in ma35d1_clocks_probe()
1010 hws[QEI0_GATE] = ma35d1_clk_gate(dev, "qei0_gate", "pclk1", in ma35d1_clocks_probe()
1012 hws[QEI1_GATE] = ma35d1_clk_gate(dev, "qei1_gate", "pclk2", in ma35d1_clocks_probe()
1014 hws[QEI2_GATE] = ma35d1_clk_gate(dev, "qei2_gate", "pclk1", in ma35d1_clocks_probe()
1017 hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(dev, "adc_div", hws[PCLK0], in ma35d1_clocks_probe()
1021 hws[ADC_GATE] = ma35d1_clk_gate(dev, "adc_gate", "adc_div", in ma35d1_clocks_probe()
1024 hws[EADC_DIV] = ma35d1_clk_divider_table(dev, "eadc_div", "pclk2", in ma35d1_clocks_probe()
1027 hws[EADC_GATE] = ma35d1_clk_gate(dev, "eadc_gate", "eadc_div", in ma35d1_clocks_probe()
1030 return devm_of_clk_add_hw_provider(dev, in ma35d1_clocks_probe()