Lines Matching refs:desc
108 const struct coreclk_soc_desc *desc) in mvebu_coreclk_setup() argument
121 clk_data.clk_num = 2 + desc->num_ratios; in mvebu_coreclk_setup()
124 if (desc->get_refclk_freq) in mvebu_coreclk_setup()
137 rate = desc->get_tclk_freq(base); in mvebu_coreclk_setup()
145 rate = desc->get_cpu_freq(base); in mvebu_coreclk_setup()
147 if (desc->is_sscg_enabled && desc->fix_sscg_deviation in mvebu_coreclk_setup()
148 && desc->is_sscg_enabled(base)) in mvebu_coreclk_setup()
149 rate = desc->fix_sscg_deviation(rate); in mvebu_coreclk_setup()
156 for (n = 0; n < desc->num_ratios; n++) { in mvebu_coreclk_setup()
157 const char *rclk_name = desc->ratios[n].name; in mvebu_coreclk_setup()
162 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); in mvebu_coreclk_setup()
169 if (desc->get_refclk_freq) { in mvebu_coreclk_setup()
172 2 + desc->num_ratios, &name); in mvebu_coreclk_setup()
173 rate = desc->get_refclk_freq(base); in mvebu_coreclk_setup()
174 clk_data.clks[2 + desc->num_ratios] = in mvebu_coreclk_setup()
176 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); in mvebu_coreclk_setup()
235 const struct clk_gating_soc_desc *desc) in mvebu_clk_gating_setup() argument
267 for (n = 0; desc[n].name;) in mvebu_clk_gating_setup()
278 (desc[n].parent) ? desc[n].parent : default_parent; in mvebu_clk_gating_setup()
279 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, in mvebu_clk_gating_setup()
280 desc[n].flags, base, desc[n].bit_idx, in mvebu_clk_gating_setup()