26 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\  argument
36 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
40 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) {	\  argument
52 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
56 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \  argument
68 		.flags = (_iflags),					\
86 		     _hi_shift, _hi_width, _pname, _iflags) {		\  argument
104 		.flags = (_iflags),					\
109 		     _pname, _iflags) {					\  argument
132 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
136 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {	\  argument
149 		.flags = (_iflags),					\
154 		    _iflags) {						\  argument
172 		.flags = (_iflags),					\