1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
25 #define CON0_ISO_EN		BIT(1)
35 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_is_prepared()  local
37 	return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;  in mtk_pll_is_prepared()
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,  in __mtk_pll_recalc_rate()  argument
43 	int pcwbits = pll->data->pcwbits;  in __mtk_pll_recalc_rate()
49 	/* The fractional part of the PLL divider. */  in __mtk_pll_recalc_rate()
50 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in __mtk_pll_recalc_rate()
52 		pcwfbits = pcwbits - ibits;  in __mtk_pll_recalc_rate()
56 	if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))  in __mtk_pll_recalc_rate()
57 		c = 1;  in __mtk_pll_recalc_rate()
64 	return ((unsigned long)vco + postdiv - 1) / postdiv;  in __mtk_pll_recalc_rate()
67 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_enable()  argument
71 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_enable()
72 		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_enable()
73 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_enable()
74 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_enable()
75 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;  in __mtk_pll_tuner_enable()
76 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_enable()
80 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_disable()  argument
84 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_disable()
85 		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_disable()
86 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_disable()
87 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_disable()
88 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;  in __mtk_pll_tuner_disable()
89 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_disable()
93 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,  in mtk_pll_set_rate_regs()  argument
99 	__mtk_pll_tuner_disable(pll);  in mtk_pll_set_rate_regs()
102 	val = readl(pll->pd_addr);  in mtk_pll_set_rate_regs()
103 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);  in mtk_pll_set_rate_regs()
104 	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;  in mtk_pll_set_rate_regs()
107 	if (pll->pd_addr != pll->pcw_addr) {  in mtk_pll_set_rate_regs()
108 		writel(val, pll->pd_addr);  in mtk_pll_set_rate_regs()
109 		val = readl(pll->pcw_addr);  in mtk_pll_set_rate_regs()
113 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,  in mtk_pll_set_rate_regs()
114 			pll->data->pcw_shift);  in mtk_pll_set_rate_regs()
115 	val |= pcw << pll->data->pcw_shift;  in mtk_pll_set_rate_regs()
116 	writel(val, pll->pcw_addr);  in mtk_pll_set_rate_regs()
117 	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;  in mtk_pll_set_rate_regs()
118 	writel(chg, pll->pcw_chg_addr);  in mtk_pll_set_rate_regs()
119 	if (pll->tuner_addr)  in mtk_pll_set_rate_regs()
120 		writel(val + 1, pll->tuner_addr);  in mtk_pll_set_rate_regs()
123 	__mtk_pll_tuner_enable(pll);  in mtk_pll_set_rate_regs()
129  * mtk_pll_calc_values - calculate good values for a given input frequency.
130  * @pll:	The pll
137 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,  in mtk_pll_calc_values()  argument
140 	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);  in mtk_pll_calc_values()
141 	const struct mtk_pll_div_table *div_table = pll->data->div_table;  in mtk_pll_calc_values()
146 	if (freq > pll->data->fmax)  in mtk_pll_calc_values()
147 		freq = pll->data->fmax;  in mtk_pll_calc_values()
153 		for (val = 0; div_table[val + 1].freq != 0; val++) {  in mtk_pll_calc_values()
154 			if (freq > div_table[val + 1].freq)  in mtk_pll_calc_values()
157 		*postdiv = 1 << val;  in mtk_pll_calc_values()
160 			*postdiv = 1 << val;  in mtk_pll_calc_values()
167 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in mtk_pll_calc_values()
168 	_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);  in mtk_pll_calc_values()
177 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_set_rate()  local
181 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);  in mtk_pll_set_rate()
182 	mtk_pll_set_rate_regs(pll, pcw, postdiv);  in mtk_pll_set_rate()
189 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_recalc_rate()  local
193 	postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;  in mtk_pll_recalc_rate()
194 	postdiv = 1 << postdiv;  in mtk_pll_recalc_rate()
196 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;  in mtk_pll_recalc_rate()
197 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);  in mtk_pll_recalc_rate()
199 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);  in mtk_pll_recalc_rate()
205 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_round_rate()  local
209 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);  in mtk_pll_round_rate()
211 	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);  in mtk_pll_round_rate()
216 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_prepare()  local
219 	r = readl(pll->pwr_addr) | CON0_PWR_ON;  in mtk_pll_prepare()
220 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
221 	udelay(1);  in mtk_pll_prepare()
223 	r = readl(pll->pwr_addr) & ~CON0_ISO_EN;  in mtk_pll_prepare()
224 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
225 	udelay(1);  in mtk_pll_prepare()
227 	r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);  in mtk_pll_prepare()
228 	writel(r, pll->en_addr);  in mtk_pll_prepare()
230 	if (pll->data->en_mask) {  in mtk_pll_prepare()
231 		r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;  in mtk_pll_prepare()
232 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
235 	__mtk_pll_tuner_enable(pll);  in mtk_pll_prepare()
239 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_prepare()
240 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
241 		r |= pll->data->rst_bar_mask;  in mtk_pll_prepare()
242 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
250 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_unprepare()  local
253 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_unprepare()
254 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
255 		r &= ~pll->data->rst_bar_mask;  in mtk_pll_unprepare()
256 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
259 	__mtk_pll_tuner_disable(pll);  in mtk_pll_unprepare()
261 	if (pll->data->en_mask) {  in mtk_pll_unprepare()
262 		r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;  in mtk_pll_unprepare()
263 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
266 	r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);  in mtk_pll_unprepare()
267 	writel(r, pll->en_addr);  in mtk_pll_unprepare()
269 	r = readl(pll->pwr_addr) | CON0_ISO_EN;  in mtk_pll_unprepare()
270 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
272 	r = readl(pll->pwr_addr) & ~CON0_PWR_ON;  in mtk_pll_unprepare()
273 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
285 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,  in mtk_clk_register_pll_ops()  argument
294 	pll->base_addr = base + data->reg;  in mtk_clk_register_pll_ops()
295 	pll->pwr_addr = base + data->pwr_reg;  in mtk_clk_register_pll_ops()
296 	pll->pd_addr = base + data->pd_reg;  in mtk_clk_register_pll_ops()
297 	pll->pcw_addr = base + data->pcw_reg;  in mtk_clk_register_pll_ops()
298 	if (data->pcw_chg_reg)  in mtk_clk_register_pll_ops()
299 		pll->pcw_chg_addr = base + data->pcw_chg_reg;  in mtk_clk_register_pll_ops()
301 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;  in mtk_clk_register_pll_ops()
302 	if (data->tuner_reg)  in mtk_clk_register_pll_ops()
303 		pll->tuner_addr = base + data->tuner_reg;  in mtk_clk_register_pll_ops()
304 	if (data->tuner_en_reg || data->tuner_en_bit)  in mtk_clk_register_pll_ops()
305 		pll->tuner_en_addr = base + data->tuner_en_reg;  in mtk_clk_register_pll_ops()
306 	if (data->en_reg)  in mtk_clk_register_pll_ops()
307 		pll->en_addr = base + data->en_reg;  in mtk_clk_register_pll_ops()
309 		pll->en_addr = pll->base_addr + REG_CON0;  in mtk_clk_register_pll_ops()
310 	pll->hw.init = &init;  in mtk_clk_register_pll_ops()
311 	pll->data = data;  in mtk_clk_register_pll_ops()
313 	init.name = data->name;  in mtk_clk_register_pll_ops()
314 	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;  in mtk_clk_register_pll_ops()
316 	if (data->parent_name)  in mtk_clk_register_pll_ops()
317 		init.parent_names = &data->parent_name;  in mtk_clk_register_pll_ops()
320 	init.num_parents = 1;  in mtk_clk_register_pll_ops()
322 	ret = clk_hw_register(NULL, &pll->hw);  in mtk_clk_register_pll_ops()
327 	return &pll->hw;  in mtk_clk_register_pll_ops()
333 	struct mtk_clk_pll *pll;  in mtk_clk_register_pll()  local
336 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in mtk_clk_register_pll()
337 	if (!pll)  in mtk_clk_register_pll()
338 		return ERR_PTR(-ENOMEM);  in mtk_clk_register_pll()
340 	hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);  in mtk_clk_register_pll()
342 		kfree(pll);  in mtk_clk_register_pll()
349 	struct mtk_clk_pll *pll;  in mtk_clk_unregister_pll()  local
354 	pll = to_mtk_clk_pll(hw);  in mtk_clk_unregister_pll()
357 	kfree(pll);  in mtk_clk_unregister_pll()
371 		return -EINVAL;  in mtk_clk_register_plls()
375 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
377 		if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {  in mtk_clk_register_plls()
379 				node, pll->id);  in mtk_clk_register_plls()
383 		hw = mtk_clk_register_pll(pll, base);  in mtk_clk_register_plls()
386 			pr_err("Failed to register clk %s: %pe\n", pll->name,  in mtk_clk_register_plls()
391 		clk_data->hws[pll->id] = hw;  in mtk_clk_register_plls()
397 	while (--i >= 0) {  in mtk_clk_register_plls()
398 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
400 		mtk_clk_unregister_pll(clk_data->hws[pll->id]);  in mtk_clk_register_plls()
401 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);  in mtk_clk_register_plls()
413 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_clk_pll_get_base()  local
415 	return pll->base_addr - data->reg;  in mtk_clk_pll_get_base()
427 	for (i = num_plls; i > 0; i--) {  in mtk_clk_unregister_plls()
428 		const struct mtk_pll_data *pll = &plls[i - 1];  in mtk_clk_unregister_plls()  local
430 		if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))  in mtk_clk_unregister_plls()
439 		base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);  in mtk_clk_unregister_plls()
441 		mtk_clk_unregister_pll(clk_data->hws[pll->id]);  in mtk_clk_unregister_plls()
442 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);  in mtk_clk_unregister_plls()