Lines Matching refs:GATE_TOP3
538 #define GATE_TOP3(_id, _name, _parent, _shift) \ macro
609 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
610 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
611 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
612 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
613 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
614 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
615 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
616 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
617 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
618 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
620 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
621 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
622 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
623 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),