Lines Matching +full:0 +full:x0d0
24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
394 0x0ec, 0, 2, 7),
396 MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1),
397 MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1),
398 MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1),
399 MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1),
400 MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1),
401 MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1),
402 MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1),
405 #define CLK_CFG_UPDATE 0x004
406 #define CLK_CFG_UPDATE1 0x008
411 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE,
412 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
413 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
414 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
415 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
416 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2),
417 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
418 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3),
420 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
421 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4),
422 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
423 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5),
425 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6),
427 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7),
429 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
430 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
431 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
432 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
434 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
435 23, CLK_CFG_UPDATE, 10, 0),
437 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
438 31, CLK_CFG_UPDATE, 11, 0),
441 msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
442 CLK_CFG_UPDATE, 12, 0),
444 msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
445 CLK_CFG_UPDATE, 13, 0),
447 msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
448 CLK_CFG_UPDATE, 14, 0),
450 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE,
454 aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7,
457 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17),
459 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE,
462 aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31,
466 aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7,
469 aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15,
472 disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23,
476 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE,
479 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
482 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
485 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE,
488 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0,
489 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
490 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
491 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29),
493 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE,
496 aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
500 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0),
501 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0,
502 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1),
503 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0,
504 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2),
505 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0,
506 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3),
509 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4),
511 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5),
512 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0,
513 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6),
514 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
515 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7),
517 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0,
518 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8),
520 gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
522 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0,
523 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10),
525 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1,
538 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
554 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
556 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
558 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
560 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
562 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
564 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
566 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
568 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
570 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
574 .set_ofs = 0,
575 .clr_ofs = 0,
576 .sta_ofs = 0,
580 .set_ofs = 0x104,
581 .clr_ofs = 0x104,
582 .sta_ofs = 0x104,
586 .set_ofs = 0x320,
587 .clr_ofs = 0x320,
588 .sta_ofs = 0x320,
614 GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
626 .set_ofs = 0x80,
627 .clr_ofs = 0x84,
628 .sta_ofs = 0x90,
632 .set_ofs = 0x88,
633 .clr_ofs = 0x8c,
634 .sta_ofs = 0x94,
638 .set_ofs = 0xa4,
639 .clr_ofs = 0xa8,
640 .sta_ofs = 0xac,
644 .set_ofs = 0xc0,
645 .clr_ofs = 0xc4,
646 .sta_ofs = 0xc8,
650 .set_ofs = 0xd0,
651 .clr_ofs = 0xd4,
652 .sta_ofs = 0xd8,
676 GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0),
712 GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0),
717 GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0),
740 GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0),
755 .set_ofs = 0x20c,
756 .clr_ofs = 0x20c,
757 .sta_ofs = 0x20c,