Lines Matching refs:MUX_GATE_CLR_SET_UPD
877 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
879 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
881 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
883 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
886 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
888 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
890 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
892 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
895 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
897 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
899 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
901 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
904 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
906 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
908 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
910 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
913 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
915 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
917 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
919 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
922 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
924 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
926 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
928 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
931 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
942 MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
944 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
946 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
953 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
955 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
960 MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
963 MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
965 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
967 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
969 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
972 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
974 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
976 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
978 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
981 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
983 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
985 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
987 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
990 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
992 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
994 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
996 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
999 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
1001 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1003 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
1005 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
1008 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
1010 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
1012 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
1014 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
1021 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1023 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1025 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1034 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1036 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1041 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1044 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
1046 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1048 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1050 MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1053 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1055 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1057 MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
1059 MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
1062 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
1064 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1066 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1068 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1071 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1073 MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
1075 MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
1077 MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
1080 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1082 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1084 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
1086 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1089 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1091 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1093 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1095 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1101 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1103 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
1105 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
1111 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
1113 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
1119 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
1121 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
1123 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1126 MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
1128 MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
1130 MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
1132 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
1135 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
1137 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1139 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1141 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1148 MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",