Lines Matching refs:MUX_GATE_CLR_SET_UPD
969 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
971 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
973 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
975 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
978 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
980 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
982 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
984 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
987 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
989 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
991 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
993 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
996 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
998 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
1000 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
1002 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
1005 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
1007 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
1009 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
1011 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
1014 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
1016 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
1027 MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
1029 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
1032 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
1034 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
1036 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
1038 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
1041 MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
1043 MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
1045 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
1047 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
1050 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
1052 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
1054 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
1056 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
1059 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
1061 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
1063 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
1065 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
1068 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
1070 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
1072 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1074 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1080 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1082 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1087 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1093 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1098 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1100 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1103 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1105 MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1107 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1109 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1112 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1114 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1116 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1118 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1121 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1123 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1125 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1127 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1130 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1132 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1134 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1136 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1139 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1141 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
1143 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
1145 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
1148 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
1150 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
1152 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
1154 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1157 MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
1159 MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
1161 MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
1163 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1170 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",