Lines Matching refs:MUX_GATE_CLR_SET_UPD
511 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
513 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
516 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
518 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
520 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
522 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
525 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
527 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
529 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
531 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
540 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
543 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
545 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "top_aud_1",
547 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "top_aud_2",
549 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1, "top_aud_engen1",
556 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2, "top_aud_engen2",
558 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "top_disp_pwm",
563 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
569 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb",
577 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
580 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
582 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
584 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
586 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
589 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
591 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
593 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
595 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
598 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
600 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
602 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1, "top_img1",
604 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
607 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "top_dpmaif",
609 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
611 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP, "top_disp",
613 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP, "top_mdp",
616 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
618 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
620 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE, "top_aes_fde",
622 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIODSP, "top_audiodsp",
631 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
633 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",
636 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
638 MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA, "top_nna",
640 MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
642 MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA2, "top_nna2",
645 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_1P, "top_ssusb_1p",
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE, "top_wpe",
654 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_250M, "top_u3_occ_250m",
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_500M, "top_u3_occ_500m",
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_BUS, "top_adsp_bus",