clk/mediatek/clk-mt8167.c

733 #define GATE_TOP2(_id, _name, _parent, _shift) \  macro
789 	GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
790 	GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
791 	GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
792 	GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
793 	GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
794 	GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
795 	GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
796 	GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
797 	GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
798 	GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
799 	GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
800 	GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
801 	GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
802 	GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
803 	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
805 	GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
806 	GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
807 	GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
808 	GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
809 	GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
810 	GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
811 	GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
812 	GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
813 	GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
814 	GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
815 	GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
816 	GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
820 	GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),