Lines Matching full:parents
294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
349 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
360 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
366 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
374 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
381 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
387 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
394 * Disabling DDR clock or its parents will render DRAM
398 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
405 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
414 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
421 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },
427 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
435 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
443 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
449 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
456 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
463 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
470 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
479 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
486 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },
492 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
499 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
507 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },
514 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
523 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
532 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
541 .parents = { JZ4780_CLK_EXCLK },
547 .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
555 .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
561 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
567 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
573 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
579 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
585 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
591 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
597 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
603 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
609 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
615 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
621 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
627 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
633 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
639 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
645 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
651 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
657 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
663 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
669 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
675 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
681 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
687 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
693 .parents = { JZ4780_CLK_LCD, -1, -1, -1 },
699 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
705 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
711 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
717 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
723 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
729 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
735 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
741 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
747 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
753 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
759 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
765 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
771 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
777 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
783 .parents = { JZ4780_CLK_CPU, -1, -1, -1 },