Lines Matching full:parents
71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
138 * Disabling MCLK or its parents will render DRAM
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
167 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
175 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
183 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
190 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
197 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
207 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
213 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
219 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
225 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
231 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
237 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
243 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
249 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },