20 #define GNRL_CTL	0x0  macro
279 	return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,  in clk_pll14xx_wait_lock()
309 	tmp = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
311 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
315 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
319 	writel(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
335 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
344 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
374 	gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
376 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
380 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
399 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
408 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
423 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
427 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
429 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
436 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
446 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_is_prepared()
460 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
462 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
528 	val = readl_relaxed(pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
530 	writel_relaxed(val, pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()