1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2017-2018 NXP.
10 #include <linux/clk-provider.h>
50 	PLL_1416X_RATE(1500000000U, 375, 3, 1),
51 	PLL_1416X_RATE(1400000000U, 350, 3, 1),
52 	PLL_1416X_RATE(1200000000U, 300, 3, 1),
53 	PLL_1416X_RATE(1000000000U, 250, 3, 1),
54 	PLL_1416X_RATE(800000000U,  200, 3, 1),
63 	PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
92 		struct clk_pll14xx *pll, unsigned long rate)  in imx_get_pll_settings()  argument
94 	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;  in imx_get_pll_settings()
97 	for (i = 0; i < pll->rate_count; i++)  in imx_get_pll_settings()
104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv,  in pll14xx_calc_rate()  argument
123 	/* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */  in pll1443x_calc_kdiv()
124 	kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);  in pll1443x_calc_kdiv()
129 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate,  in imx_pll14xx_calc_settings()  argument
138 	 * Fractional PLL constrains:  in imx_pll14xx_calc_settings()
140 	 * a) 1 <= p <= 63  in imx_pll14xx_calc_settings()
143 	 * d) -32768 <= k <= 32767  in imx_pll14xx_calc_settings()
149 	tt = imx_get_pll_settings(pll, rate);  in imx_pll14xx_calc_settings()
151 		pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",  in imx_pll14xx_calc_settings()
152 			 clk_hw_get_name(&pll->hw), prate, rate);  in imx_pll14xx_calc_settings()
153 		t->rate = tt->rate;  in imx_pll14xx_calc_settings()
154 		t->mdiv = tt->mdiv;  in imx_pll14xx_calc_settings()
155 		t->pdiv = tt->pdiv;  in imx_pll14xx_calc_settings()
156 		t->sdiv = tt->sdiv;  in imx_pll14xx_calc_settings()
157 		t->kdiv = tt->kdiv;  in imx_pll14xx_calc_settings()
161 	pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);  in imx_pll14xx_calc_settings()
165 	pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);  in imx_pll14xx_calc_settings()
168 	rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate);  in imx_pll14xx_calc_settings()
169 	rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate);  in imx_pll14xx_calc_settings()
173 		pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",  in imx_pll14xx_calc_settings()
174 			 clk_hw_get_name(&pll->hw), prate, rate,  in imx_pll14xx_calc_settings()
176 		fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);  in imx_pll14xx_calc_settings()
177 		t->rate = (unsigned int)fvco;  in imx_pll14xx_calc_settings()
178 		t->mdiv = mdiv;  in imx_pll14xx_calc_settings()
179 		t->pdiv = pdiv;  in imx_pll14xx_calc_settings()
180 		t->sdiv = sdiv;  in imx_pll14xx_calc_settings()
181 		t->kdiv = kdiv;  in imx_pll14xx_calc_settings()
186 	for (pdiv = 1; pdiv <= 63; pdiv++) {  in imx_pll14xx_calc_settings()
193 			fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);  in imx_pll14xx_calc_settings()
196 			dist = abs((long)rate - (long)fvco);  in imx_pll14xx_calc_settings()
199 				t->rate = (unsigned int)fvco;  in imx_pll14xx_calc_settings()
200 				t->mdiv = mdiv;  in imx_pll14xx_calc_settings()
201 				t->pdiv = pdiv;  in imx_pll14xx_calc_settings()
202 				t->sdiv = sdiv;  in imx_pll14xx_calc_settings()
203 				t->kdiv = kdiv;  in imx_pll14xx_calc_settings()
212 		 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,  in imx_pll14xx_calc_settings()
213 		 t->mdiv, t->kdiv);  in imx_pll14xx_calc_settings()
219 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1416x_round_rate()  local
220 	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;  in clk_pll1416x_round_rate()
224 	for (i = 0; i < pll->rate_count; i++)  in clk_pll1416x_round_rate()
229 	return rate_table[pll->rate_count - 1].rate;  in clk_pll1416x_round_rate()
235 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1443x_round_rate()  local
238 	imx_pll14xx_calc_settings(pll, rate, *prate, &t);  in clk_pll1443x_round_rate()
246 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_recalc_rate()  local
249 	pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);  in clk_pll14xx_recalc_rate()
254 	if (pll->type == PLL_1443X) {  in clk_pll14xx_recalc_rate()
255 		pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);  in clk_pll14xx_recalc_rate()
261 	return pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, parent_rate);  in clk_pll14xx_recalc_rate()
272 	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;  in clk_pll14xx_mp_change()
275 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)  in clk_pll14xx_wait_lock()  argument
279 	return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,  in clk_pll14xx_wait_lock()
286 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1416x_set_rate()  local
291 	rate = imx_get_pll_settings(pll, drate);  in clk_pll1416x_set_rate()
293 		pr_err("Invalid rate %lu for pll clk %s\n", drate,  in clk_pll1416x_set_rate()
295 		return -EINVAL;  in clk_pll1416x_set_rate()
298 	tmp = readl_relaxed(pll->base + DIV_CTL0);  in clk_pll1416x_set_rate()
302 		tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);  in clk_pll1416x_set_rate()
303 		writel_relaxed(tmp, pll->base + DIV_CTL0);  in clk_pll1416x_set_rate()
308 	/* Bypass clock and set lock to pll output lock */  in clk_pll1416x_set_rate()
309 	tmp = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
311 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
315 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
319 	writel(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
321 	div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) |  in clk_pll1416x_set_rate()
322 		FIELD_PREP(SDIV_MASK, rate->sdiv);  in clk_pll1416x_set_rate()
323 	writel_relaxed(div_val, pll->base + DIV_CTL0);  in clk_pll1416x_set_rate()
326 	 * According to SPEC, t3 - t2 need to be greater than  in clk_pll1416x_set_rate()
327 	 * 1us and 1/FREF, respectively.  in clk_pll1416x_set_rate()
328 	 * FREF is FIN / Prediv, the prediv is [1, 63], so choose  in clk_pll1416x_set_rate()
335 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
338 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll1416x_set_rate()
344 	writel_relaxed(tmp, pll->base + GNRL_CTL);  in clk_pll1416x_set_rate()
352 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll1443x_set_rate()  local
357 	imx_pll14xx_calc_settings(pll, drate, prate, &rate);  in clk_pll1443x_set_rate()
359 	div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);  in clk_pll1443x_set_rate()
362 		/* only sdiv and/or kdiv changed - no need to RESET PLL */  in clk_pll1443x_set_rate()
365 		writel_relaxed(div_ctl0, pll->base + DIV_CTL0);  in clk_pll1443x_set_rate()
368 			       pll->base + DIV_CTL1);  in clk_pll1443x_set_rate()
374 	gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
376 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
380 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
385 	writel_relaxed(div_ctl0, pll->base + DIV_CTL0);  in clk_pll1443x_set_rate()
387 	writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1);  in clk_pll1443x_set_rate()
390 	 * According to SPEC, t3 - t2 need to be greater than  in clk_pll1443x_set_rate()
391 	 * 1us and 1/FREF, respectively.  in clk_pll1443x_set_rate()
392 	 * FREF is FIN / Prediv, the prediv is [1, 63], so choose  in clk_pll1443x_set_rate()
399 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
402 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll1443x_set_rate()
408 	writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);  in clk_pll1443x_set_rate()
415 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_prepare()  local
420 	 * RESETB = 1 from 0, PLL starts its normal  in clk_pll14xx_prepare()
423 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
427 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
429 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
431 	ret = clk_pll14xx_wait_lock(pll);  in clk_pll14xx_prepare()
436 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_prepare()
443 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_is_prepared()  local
446 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_is_prepared()
448 	return (val & RST_MASK) ? 1 : 0;  in clk_pll14xx_is_prepared()
453 	struct clk_pll14xx *pll = to_clk_pll14xx(hw);  in clk_pll14xx_unprepare()  local
460 	val = readl_relaxed(pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
462 	writel_relaxed(val, pll->base + GNRL_CTL);  in clk_pll14xx_unprepare()
491 	struct clk_pll14xx *pll;  in imx_dev_clk_hw_pll14xx()  local
497 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_dev_clk_hw_pll14xx()
498 	if (!pll)  in imx_dev_clk_hw_pll14xx()
499 		return ERR_PTR(-ENOMEM);  in imx_dev_clk_hw_pll14xx()
502 	init.flags = pll_clk->flags;  in imx_dev_clk_hw_pll14xx()
504 	init.num_parents = 1;  in imx_dev_clk_hw_pll14xx()
506 	switch (pll_clk->type) {  in imx_dev_clk_hw_pll14xx()
508 		if (!pll_clk->rate_table)  in imx_dev_clk_hw_pll14xx()
517 		pr_err("Unknown pll type for pll clk %s\n", name);  in imx_dev_clk_hw_pll14xx()
518 		kfree(pll);  in imx_dev_clk_hw_pll14xx()
519 		return ERR_PTR(-EINVAL);  in imx_dev_clk_hw_pll14xx()
522 	pll->base = base;  in imx_dev_clk_hw_pll14xx()
523 	pll->hw.init = &init;  in imx_dev_clk_hw_pll14xx()
524 	pll->type = pll_clk->type;  in imx_dev_clk_hw_pll14xx()
525 	pll->rate_table = pll_clk->rate_table;  in imx_dev_clk_hw_pll14xx()
526 	pll->rate_count = pll_clk->rate_count;  in imx_dev_clk_hw_pll14xx()
528 	val = readl_relaxed(pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
530 	writel_relaxed(val, pll->base + GNRL_CTL);  in imx_dev_clk_hw_pll14xx()
532 	hw = &pll->hw;  in imx_dev_clk_hw_pll14xx()
536 		pr_err("failed to register pll %s %d\n", name, ret);  in imx_dev_clk_hw_pll14xx()
537 		kfree(pll);  in imx_dev_clk_hw_pll14xx()