1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
20 #define CLKMUX_EN		BIT(1)
82 	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
83 	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
84 	PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
85 	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
86 	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
87 	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
88 	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
90 	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
106 	PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
107 	PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
108 	PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
123 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)  in imx_get_pll_settings()  argument
125 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in imx_get_pll_settings()
128 	for (i = 0; i < pll->rate_count; i++)  in imx_get_pll_settings()
138 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_round_rate()  local
139 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in clk_fracn_gppll_round_rate()
143 	for (i = 0; i < pll->rate_count; i++)  in clk_fracn_gppll_round_rate()
148 	return rate_table[pll->rate_count - 1].rate;  in clk_fracn_gppll_round_rate()
153 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_recalc_rate()  local
154 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in clk_fracn_gppll_recalc_rate()
161 	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_recalc_rate()
164 	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);  in clk_fracn_gppll_recalc_rate()
167 	pll_div = readl_relaxed(pll->base + PLL_DIV);  in clk_fracn_gppll_recalc_rate()
175 	 * the frac part. So find the accurate pll rate from the table  in clk_fracn_gppll_recalc_rate()
179 	for (i = 0; i < pll->rate_count; i++) {  in clk_fracn_gppll_recalc_rate()
190 		rdiv = rdiv + 1;  in clk_fracn_gppll_recalc_rate()
196 	case 1:  in clk_fracn_gppll_recalc_rate()
203 	if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {  in clk_fracn_gppll_recalc_rate()
216 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)  in clk_fracn_gppll_wait_lock()  argument
220 	return readl_poll_timeout(pll->base + PLL_STATUS, val,  in clk_fracn_gppll_wait_lock()
227 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_set_rate()  local
232 	rate = imx_get_pll_settings(pll, drate);  in clk_fracn_gppll_set_rate()
234 	/* Hardware control select disable. PLL is control by register */  in clk_fracn_gppll_set_rate()
235 	tmp = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
237 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
240 	tmp = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
242 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
246 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
250 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
252 	pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |  in clk_fracn_gppll_set_rate()
253 		FIELD_PREP(PLL_MFI_MASK, rate->mfi);  in clk_fracn_gppll_set_rate()
254 	writel_relaxed(pll_div, pll->base + PLL_DIV);  in clk_fracn_gppll_set_rate()
255 	readl(pll->base + PLL_DIV);  in clk_fracn_gppll_set_rate()
256 	if (pll->flags & CLK_FRACN_GPPLL_FRACN) {  in clk_fracn_gppll_set_rate()
257 		writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);  in clk_fracn_gppll_set_rate()
258 		writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_set_rate()
259 		readl(pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_set_rate()
262 	/* Wait for 5us according to fracn mode pll doc */  in clk_fracn_gppll_set_rate()
267 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
268 	readl(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
271 	ret = clk_fracn_gppll_wait_lock(pll);  in clk_fracn_gppll_set_rate()
277 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
279 	ana_mfn = readl_relaxed(pll->base + PLL_STATUS);  in clk_fracn_gppll_set_rate()
282 	WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");  in clk_fracn_gppll_set_rate()
289 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_prepare()  local
293 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
297 	if (pll->flags & CLK_FRACN_GPPLL_FRACN)  in clk_fracn_gppll_prepare()
298 		writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),  in clk_fracn_gppll_prepare()
299 			       pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_prepare()
302 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
305 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
306 	readl(pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
308 	ret = clk_fracn_gppll_wait_lock(pll);  in clk_fracn_gppll_prepare()
313 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
316 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
323 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_is_prepared()  local
326 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_is_prepared()
328 	return (val & POWERUP_MASK) ? 1 : 0;  in clk_fracn_gppll_is_prepared()
333 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_unprepare()  local
336 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_unprepare()
338 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_unprepare()
355 	struct clk_fracn_gppll *pll;  in _imx_clk_fracn_gppll()  local
360 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in _imx_clk_fracn_gppll()
361 	if (!pll)  in _imx_clk_fracn_gppll()
362 		return ERR_PTR(-ENOMEM);  in _imx_clk_fracn_gppll()
365 	init.flags = pll_clk->flags;  in _imx_clk_fracn_gppll()
367 	init.num_parents = 1;  in _imx_clk_fracn_gppll()
370 	pll->base = base;  in _imx_clk_fracn_gppll()
371 	pll->hw.init = &init;  in _imx_clk_fracn_gppll()
372 	pll->rate_table = pll_clk->rate_table;  in _imx_clk_fracn_gppll()
373 	pll->rate_count = pll_clk->rate_count;  in _imx_clk_fracn_gppll()
374 	pll->flags = pll_flags;  in _imx_clk_fracn_gppll()
376 	hw = &pll->hw;  in _imx_clk_fracn_gppll()
380 		pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);  in _imx_clk_fracn_gppll()
381 		kfree(pll);  in _imx_clk_fracn_gppll()