Lines Matching full:divider
31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
110 val = orig & ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
113 val |= (u32)(prediv_value - 1) << divider->shift; in imx8m_clk_composite_divider_set_rate()
117 writel(val, divider->reg); in imx8m_clk_composite_divider_set_rate()
119 spin_unlock_irqrestore(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
127 struct clk_divider *divider = to_clk_divider(hw); in imx8m_divider_determine_rate() local
132 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in imx8m_divider_determine_rate()
135 val = readl(divider->reg); in imx8m_divider_determine_rate()
136 prediv_value = val >> divider->shift; in imx8m_divider_determine_rate()
137 prediv_value &= clk_div_mask(divider->width); in imx8m_divider_determine_rate()
144 return divider_ro_determine_rate(hw, req, divider->table, in imx8m_divider_determine_rate()
146 divider->flags, prediv_value * div_value); in imx8m_divider_determine_rate()
149 return divider_determine_rate(hw, req, divider->table, in imx8m_divider_determine_rate()
151 divider->flags); in imx8m_divider_determine_rate()