Lines Matching refs:CLK_SET_RATE_PARENT
76 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
79 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
82 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
84 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
93 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
96 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
103 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
110 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
112 CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
114 CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
117 CLK_SET_RATE_PARENT, 0x70, 0, 0, },
120 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
122 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
125 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
127 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
130 CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
132 CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
134 CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
136 CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
139 CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
141 CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
143 CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
145 CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
147 CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
149 CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
151 CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
153 CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
156 CLK_SET_RATE_PARENT, 0x188, 0, 0, },
159 CLK_SET_RATE_PARENT, 0x188, 8, 0, },
162 CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
164 CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
166 CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
168 CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
170 CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
172 CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
174 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
176 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
179 CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
181 CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
183 CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
185 CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
187 CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
189 CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
191 CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
193 CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
282 CLK_SET_RATE_PARENT, 0x48, 4, 0, },
284 CLK_SET_RATE_PARENT, 0x48, 6, 0, },
286 CLK_SET_RATE_PARENT, 0x48, 10, 0, },