Lines Matching refs:CLK_SET_RATE_PARENT
70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
89 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
91 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
94 { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
96 { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
99 { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
101 { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
103 { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
105 { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
107 { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
113 { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
200 CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },