clk/hisilicon/clk-hi3559a.c

142 		CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
146 		CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
150 		CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
155 		CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
160 		CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
165 		CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
170 		CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
175 		CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
180 		CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
187 		CLK_SET_RATE_PARENT, 0x170, 1, 0,
191 		CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
195 		CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
199 		CLK_SET_RATE_PARENT, 0x214, 28, 0,
203 		CLK_SET_RATE_PARENT, 0x23c, 28, 0,
207 		CLK_SET_RATE_PARENT, 0x198, 23, 0,
211 		CLK_SET_RATE_PARENT, 0x198, 24, 0,
215 		CLK_SET_RATE_PARENT, 0x198, 25, 0,
219 		CLK_SET_RATE_PARENT, 0x198, 26, 0,
223 		CLK_SET_RATE_PARENT, 0x198, 27, 0,
227 		CLK_SET_RATE_PARENT, 0x0174, 1, 0,
231 		CLK_SET_RATE_PARENT, 0x0174, 5, 0,
235 		CLK_SET_RATE_PARENT, 0x0174, 3, 0,
239 		CLK_SET_RATE_PARENT, 0x0174, 7, 0,
243 		CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
247 		CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
251 		CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
255 		CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
259 		CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
263 		CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
267 		CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
271 		CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
275 		CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
279 		CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
283 		CLK_SET_RATE_PARENT, 0x01a0, 26, 0,
287 		CLK_SET_RATE_PARENT, 0x01a0, 27, 0,
291 		CLK_SET_RATE_PARENT, 0x0198, 16, 0,
295 		CLK_SET_RATE_PARENT, 0x0198, 17, 0,
299 		CLK_SET_RATE_PARENT, 0x0198, 18, 0,
303 		CLK_SET_RATE_PARENT, 0x0198, 19, 0,
307 		CLK_SET_RATE_PARENT, 0x0198, 20, 0,
311 		CLK_SET_RATE_PARENT, 0x0198, 21, 0,
315 		CLK_SET_RATE_PARENT, 0x0198, 22, 0,
319 		CLK_SET_RATE_PARENT, 0x16c, 6, 0,
323 		CLK_SET_RATE_PARENT, 0x16c, 5, 0,
327 		CLK_SET_RATE_PARENT, 0x16c, 9, 0,
331 		CLK_SET_RATE_PARENT, 0x16c, 8, 0,
335 		CLK_SET_RATE_PARENT, 0x14c, 5, 0,