Lines Matching refs:div_data
487 const struct vc3_div_data *div_data = vc3->data; in vc3_div_recalc_rate() local
490 regmap_read(vc3->regmap, div_data->offs, &val); in vc3_div_recalc_rate()
491 val >>= div_data->shift; in vc3_div_recalc_rate()
492 val &= VC3_DIV_MASK(div_data->width); in vc3_div_recalc_rate()
494 return divider_recalc_rate(hw, parent_rate, val, div_data->table, in vc3_div_recalc_rate()
495 div_data->flags, div_data->width); in vc3_div_recalc_rate()
502 const struct vc3_div_data *div_data = vc3->data; in vc3_div_round_rate() local
506 if (div_data->flags & CLK_DIVIDER_READ_ONLY) { in vc3_div_round_rate()
507 regmap_read(vc3->regmap, div_data->offs, &bestdiv); in vc3_div_round_rate()
508 bestdiv >>= div_data->shift; in vc3_div_round_rate()
509 bestdiv &= VC3_DIV_MASK(div_data->width); in vc3_div_round_rate()
510 bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags); in vc3_div_round_rate()
514 return divider_round_rate(hw, rate, parent_rate, div_data->table, in vc3_div_round_rate()
515 div_data->width, div_data->flags); in vc3_div_round_rate()
522 const struct vc3_div_data *div_data = vc3->data; in vc3_div_set_rate() local
525 value = divider_get_val(rate, parent_rate, div_data->table, in vc3_div_set_rate()
526 div_data->width, div_data->flags); in vc3_div_set_rate()
527 regmap_update_bits(vc3->regmap, div_data->offs, in vc3_div_set_rate()
528 VC3_DIV_MASK(div_data->width) << div_data->shift, in vc3_div_set_rate()
529 value << div_data->shift); in vc3_div_set_rate()