25 #define PLL_DIV2	1  macro
125 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
134 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
141 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
150 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
157 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
159 		[5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
166 		[1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
168 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
175 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
177 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
186 		[9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
188 		[13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
195 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
202 		[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
204 		[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
212 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
216 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
220 		{ CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
228 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
232 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
240 		{ CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
244 		{ CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
252 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
261 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
265 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
274 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
278 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
287 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
291 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
300 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
304 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
313 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
317 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
335 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
339 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
348 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
352 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
360 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
364 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
373 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
377 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
386 		[2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
394 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
401 		[6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
409 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
413 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
422 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
426 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
433 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
435 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
439 		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
446 		[2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
450 		[6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
456 		[2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
460 		[6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
476 		cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;  in p2041_init_periph()
478 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p2041_init_periph()
488 		cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
490 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
493 		cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
495 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
501 	int div = PLL_DIV2;  in p5020_init_periph()
510 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5020_init_periph()
516 	int div = PLL_DIV2;  in p5040_init_periph()
525 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
530 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()