1 // SPDX-License-Identifier: GPL-2.0
3  * Nuvoton NPCM8xx Clock Generator
15 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
24 #include <soc/nuvoton/clock-npcm8xx.h>
26 /* npcm8xx clock registers*/
190 	{ NPCM8XX_CLKDIV1, 21, 5, "pre_adc", &npcm8xx_muxes[6].hw, CLK_DIVIDER_READ_ONLY, 0, -1 },
237 	val = readl_relaxed(pll->pllcon);  in npcm8xx_clk_pll_recalc_rate()
265 		return ERR_PTR(-ENOMEM);  in npcm8xx_clk_register_pll()
273 	pll->pllcon = pllcon;  in npcm8xx_clk_register_pll()
274 	pll->hw.init = &init;  in npcm8xx_clk_register_pll()
276 	ret = devm_clk_hw_register(dev, &pll->hw);  in npcm8xx_clk_register_pll()
280 	return &pll->hw;  in npcm8xx_clk_register_pll()
290 	struct device *dev = &adev->dev;  in npcm8xx_clk_probe()
298 		return -ENOMEM;  in npcm8xx_clk_probe()
300 	clk_base = rdev->base;  in npcm8xx_clk_probe()
302 	npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;  in npcm8xx_clk_probe()
305 		npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);  in npcm8xx_clk_probe()
311 		hw = npcm8xx_clk_register_pll(dev, clk_base + pll_clk->reg,  in npcm8xx_clk_probe()
312 					      pll_clk->name, &pll_clk->parent,  in npcm8xx_clk_probe()
313 					      pll_clk->flags);  in npcm8xx_clk_probe()
316 		pll_clk->hw = *hw;  in npcm8xx_clk_probe()
340 								mux_data->name,  in npcm8xx_clk_probe()
341 								mux_data->parent_data,  in npcm8xx_clk_probe()
342 								mux_data->num_parents,  in npcm8xx_clk_probe()
343 								mux_data->flags,  in npcm8xx_clk_probe()
345 								mux_data->shift,  in npcm8xx_clk_probe()
346 								mux_data->mask,  in npcm8xx_clk_probe()
348 								mux_data->table,  in npcm8xx_clk_probe()
352 		mux_data->hw = *hw;  in npcm8xx_clk_probe()
363 	npcm8xx_clk_data->hws[NPCM8XX_CLK_AXI] = hw;  in npcm8xx_clk_probe()
368 	npcm8xx_clk_data->hws[NPCM8XX_CLK_ATB] = hw;  in npcm8xx_clk_probe()
374 		hw = devm_clk_hw_register_divider_parent_hw(dev, div_data->name,  in npcm8xx_clk_probe()
375 							    div_data->parent_hw,  in npcm8xx_clk_probe()
376 							    div_data->flags,  in npcm8xx_clk_probe()
377 							    clk_base + div_data->reg,  in npcm8xx_clk_probe()
378 							    div_data->shift,  in npcm8xx_clk_probe()
379 							    div_data->width,  in npcm8xx_clk_probe()
380 							    div_data->clk_divider_flags,  in npcm8xx_clk_probe()
384 		div_data->hw = *hw;  in npcm8xx_clk_probe()
386 		if (div_data->onecell_idx >= 0)  in npcm8xx_clk_probe()
387 			npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;  in npcm8xx_clk_probe()
394 		hw = devm_clk_hw_register_divider_parent_hw(dev, div_data->name,  in npcm8xx_clk_probe()
395 							    div_data->parent_hw,  in npcm8xx_clk_probe()
396 							    div_data->flags,  in npcm8xx_clk_probe()
397 							    clk_base + div_data->reg,  in npcm8xx_clk_probe()
398 							    div_data->shift,  in npcm8xx_clk_probe()
399 							    div_data->width,  in npcm8xx_clk_probe()
400 							    div_data->clk_divider_flags,  in npcm8xx_clk_probe()
405 		if (div_data->onecell_idx >= 0)  in npcm8xx_clk_probe()
406 			npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;  in npcm8xx_clk_probe()
415 		.name = "reset_npcm.clk-npcm8xx",
427 MODULE_DESCRIPTION("Clock driver for Nuvoton NPCM8XX BMC SoC");