clk/bcm/clk-cygnus.c

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
23 #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \  argument
24 		{ .offset = o, .en_shift = es, .high_shift = hs, \
36 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \  argument
39 #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }  argument
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
65 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
71 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
77 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
83 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
89 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
95 		.enable = ENABLE_VAL(0x4, 11, 5, 17),
105 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
123 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
129 		.enable = ENABLE_VAL(0x0, 8, 2, 14),
135 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
141 		.enable = ENABLE_VAL(0x0, 10, 4, 16),
147 		.enable = ENABLE_VAL(0x0, 11, 5, 17),
153 		.enable = ENABLE_VAL(0x0, 12, 6, 18),
163 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
201 		.enable = ENABLE_VAL(0x4, 12, 6, 18),
207 		.enable = ENABLE_VAL(0x4, 13, 7, 19),
213 		.enable = ENABLE_VAL(0x4, 14, 8, 20),
219 		.enable = ENABLE_VAL(0x4, 15, 9, 21),
225 		.enable = ENABLE_VAL(0x4, 16, 10, 22),
231 		.enable = ENABLE_VAL(0x4, 17, 11, 23),
242 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
260 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
281 		.enable = ENABLE_VAL(0x14, 8, 10, 9),
287 		.enable = ENABLE_VAL(0x18, 8, 10, 9),
293 		.enable = ENABLE_VAL(0x1c, 8, 10, 9),
303 CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",