41 	struct sam9x60_pll_core core;  member
48 	struct sam9x60_pll_core core;  member
55 #define to_sam9x60_frac(core)	container_of(core, struct sam9x60_frac, core)  argument
56 #define to_sam9x60_div(core)	container_of(core, struct sam9x60_div, core)  argument
77 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_recalc_rate()  local
78 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_recalc_rate()
84 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)  in sam9x60_frac_pll_set()  argument
86 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_set()
87 	struct regmap *regmap = core->regmap;  in sam9x60_frac_pll_set()
91 	spin_lock_irqsave(core->lock, flags);  in sam9x60_frac_pll_set()
94 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_frac_pll_set()
96 	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;  in sam9x60_frac_pll_set()
97 	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;  in sam9x60_frac_pll_set()
99 	if (sam9x60_frac_pll_ready(regmap, core->id) &&  in sam9x60_frac_pll_set()
104 	if (core->characteristics->upll)  in sam9x60_frac_pll_set()
111 		     (frac->mul << core->layout->mul_shift) |  in sam9x60_frac_pll_set()
112 		     (frac->frac << core->layout->frac_shift));  in sam9x60_frac_pll_set()
114 	if (core->characteristics->upll) {  in sam9x60_frac_pll_set()
130 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set()
138 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set()
140 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_frac_pll_set()
144 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_frac_pll_set()
151 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_prepare()  local
153 	return sam9x60_frac_pll_set(core);  in sam9x60_frac_pll_prepare()
158 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_unprepare()  local
159 	struct regmap *regmap = core->regmap;  in sam9x60_frac_pll_unprepare()
162 	spin_lock_irqsave(core->lock, flags);  in sam9x60_frac_pll_unprepare()
165 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_frac_pll_unprepare()
169 	if (core->characteristics->upll)  in sam9x60_frac_pll_unprepare()
175 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_unprepare()
177 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_frac_pll_unprepare()
182 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_is_prepared()  local
184 	return sam9x60_pll_ready(core->regmap, core->id);  in sam9x60_frac_pll_is_prepared()
187 static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,  in sam9x60_frac_pll_compute_mul_frac()  argument
192 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_compute_mul_frac()
231 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_round_rate()  local
233 	return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);  in sam9x60_frac_pll_round_rate()
239 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_set_rate()  local
241 	return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);  in sam9x60_frac_pll_set_rate()
247 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_set_rate_chg()  local
248 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_set_rate_chg()
249 	struct regmap *regmap = core->regmap;  in sam9x60_frac_pll_set_rate_chg()
254 	ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);  in sam9x60_frac_pll_set_rate_chg()
258 	spin_lock_irqsave(core->lock, irqflags);  in sam9x60_frac_pll_set_rate_chg()
261 			   core->id);  in sam9x60_frac_pll_set_rate_chg()
263 	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;  in sam9x60_frac_pll_set_rate_chg()
264 	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;  in sam9x60_frac_pll_set_rate_chg()
270 		     (frac->mul << core->layout->mul_shift) |  in sam9x60_frac_pll_set_rate_chg()
271 		     (frac->frac << core->layout->frac_shift));  in sam9x60_frac_pll_set_rate_chg()
275 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set_rate_chg()
284 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set_rate_chg()
286 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_frac_pll_set_rate_chg()
290 	spin_unlock_irqrestore(core->lock, irqflags);  in sam9x60_frac_pll_set_rate_chg()
297 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_save_context()  local
298 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_save_context()
300 	frac->pms.status = sam9x60_pll_ready(core->regmap, core->id);  in sam9x60_frac_pll_save_context()
307 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_frac_pll_restore_context()  local
308 	struct sam9x60_frac *frac = to_sam9x60_frac(core);  in sam9x60_frac_pll_restore_context()
311 		sam9x60_frac_pll_set(core);  in sam9x60_frac_pll_restore_context()
337 static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,  in sam9x60_div_pll_set_div()  argument
340 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_set_div()
341 	u32 ena_msk = enable ? core->layout->endiv_mask : 0;  in sam9x60_div_pll_set_div()
342 	u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;  in sam9x60_div_pll_set_div()
345 			   core->layout->div_mask | ena_msk,  in sam9x60_div_pll_set_div()
346 			   (div << core->layout->div_shift) | ena_val);  in sam9x60_div_pll_set_div()
350 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_set_div()
352 	while (!sam9x60_pll_ready(regmap, core->id))  in sam9x60_div_pll_set_div()
356 static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)  in sam9x60_div_pll_set()  argument
358 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_set()
359 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_set()
363 	spin_lock_irqsave(core->lock, flags);  in sam9x60_div_pll_set()
365 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_div_pll_set()
367 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set()
370 	if (!!(val & core->layout->endiv_mask) && cdiv == div->div)  in sam9x60_div_pll_set()
373 	sam9x60_div_pll_set_div(core, div->div, 1);  in sam9x60_div_pll_set()
376 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_div_pll_set()
383 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_prepare()  local
385 	return sam9x60_div_pll_set(core);  in sam9x60_div_pll_prepare()
390 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_unprepare()  local
391 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_unprepare()
394 	spin_lock_irqsave(core->lock, flags);  in sam9x60_div_pll_unprepare()
397 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_div_pll_unprepare()
400 			   core->layout->endiv_mask, 0);  in sam9x60_div_pll_unprepare()
404 			   AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_unprepare()
406 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_div_pll_unprepare()
411 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_is_prepared()  local
412 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_is_prepared()
416 	spin_lock_irqsave(core->lock, flags);  in sam9x60_div_pll_is_prepared()
419 			   AT91_PMC_PLL_UPDT_ID_MSK, core->id);  in sam9x60_div_pll_is_prepared()
422 	spin_unlock_irqrestore(core->lock, flags);  in sam9x60_div_pll_is_prepared()
424 	return !!(val & core->layout->endiv_mask);  in sam9x60_div_pll_is_prepared()
430 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_recalc_rate()  local
431 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_recalc_rate()
436 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,  in sam9x60_div_pll_compute_div()  argument
441 							core->characteristics;  in sam9x60_div_pll_compute_div()
442 	struct clk_hw *parent = clk_hw_get_parent(&core->hw);  in sam9x60_div_pll_compute_div()
454 	for (divid = 1; divid < core->layout->div_mask; divid++) {  in sam9x60_div_pll_compute_div()
482 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_round_rate()  local
484 	return sam9x60_div_pll_compute_div(core, parent_rate, rate);  in sam9x60_div_pll_round_rate()
490 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_set_rate()  local
491 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_set_rate()
501 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_set_rate_chg()  local
502 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_set_rate_chg()
503 	struct regmap *regmap = core->regmap;  in sam9x60_div_pll_set_rate_chg()
509 	spin_lock_irqsave(core->lock, irqflags);  in sam9x60_div_pll_set_rate_chg()
511 			   core->id);  in sam9x60_div_pll_set_rate_chg()
513 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set_rate_chg()
519 	sam9x60_div_pll_set_div(core, div->div, 0);  in sam9x60_div_pll_set_rate_chg()
522 	spin_unlock_irqrestore(core->lock, irqflags);  in sam9x60_div_pll_set_rate_chg()
529 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_save_context()  local
530 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_save_context()
539 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);  in sam9x60_div_pll_restore_context()  local
540 	struct sam9x60_div *div = to_sam9x60_div(core);  in sam9x60_div_pll_restore_context()
543 		sam9x60_div_pll_set(core);  in sam9x60_div_pll_restore_context()
550 	struct sam9x60_pll_core core = div->core;  in sam9x60_div_pll_notifier_fn()  local
551 	struct regmap *regmap = core.regmap;  in sam9x60_div_pll_notifier_fn()
565 	spin_lock_irqsave(core.lock, irqflags);  in sam9x60_div_pll_notifier_fn()
567 			   core.id);  in sam9x60_div_pll_notifier_fn()
569 	cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;  in sam9x60_div_pll_notifier_fn()
575 	sam9x60_div_pll_set_div(&core, div->div, 0);  in sam9x60_div_pll_notifier_fn()
579 	spin_unlock_irqrestore(core.lock, irqflags);  in sam9x60_div_pll_notifier_fn()
644 	frac->core.id = id;  in sam9x60_clk_register_frac_pll()
645 	frac->core.hw.init = &init;  in sam9x60_clk_register_frac_pll()
646 	frac->core.characteristics = characteristics;  in sam9x60_clk_register_frac_pll()
647 	frac->core.layout = layout;  in sam9x60_clk_register_frac_pll()
648 	frac->core.regmap = regmap;  in sam9x60_clk_register_frac_pll()
649 	frac->core.lock = lock;  in sam9x60_clk_register_frac_pll()
651 	spin_lock_irqsave(frac->core.lock, irqflags);  in sam9x60_clk_register_frac_pll()
672 		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,  in sam9x60_clk_register_frac_pll()
679 	spin_unlock_irqrestore(frac->core.lock, irqflags);  in sam9x60_clk_register_frac_pll()
681 	hw = &frac->core.hw;  in sam9x60_clk_register_frac_pll()
691 	spin_unlock_irqrestore(frac->core.lock, irqflags);  in sam9x60_clk_register_frac_pll()
734 	div->core.id = id;  in sam9x60_clk_register_div_pll()
735 	div->core.hw.init = &init;  in sam9x60_clk_register_div_pll()
736 	div->core.characteristics = characteristics;  in sam9x60_clk_register_div_pll()
737 	div->core.layout = layout;  in sam9x60_clk_register_div_pll()
738 	div->core.regmap = regmap;  in sam9x60_clk_register_div_pll()
739 	div->core.lock = lock;  in sam9x60_clk_register_div_pll()
742 	spin_lock_irqsave(div->core.lock, irqflags);  in sam9x60_clk_register_div_pll()
749 	spin_unlock_irqrestore(div->core.lock, irqflags);  in sam9x60_clk_register_div_pll()
751 	hw = &div->core.hw;  in sam9x60_clk_register_div_pll()