Lines Matching refs:OWL_DIVIDER_HW

225 			OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
231 			OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
261 			OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
285 			OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
291 			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
297 			OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9,  CLK_DIVIDER_ROUND_CLOSEST, NULL),
303 			OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9,  CLK_DIVIDER_ROUND_CLOSEST, NULL),
309 			OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9,  CLK_DIVIDER_ROUND_CLOSEST, NULL),
315 			OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9,  CLK_DIVIDER_ROUND_CLOSEST, NULL),
321 			OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9,  CLK_DIVIDER_ROUND_CLOSEST, NULL),
327 			OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
333 			OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
339 			OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
345 			OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
351 			OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
357 			OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
375 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
381 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
387 			OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
398 			OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
407 				OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),