145 #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)  macro
338 	SET_PORT_BITS(TLCLK_REG1, 0xef, val);  in store_received_ref_clk3a()
360 	SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1);  in store_received_ref_clk3b()
382 	SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);  in store_enable_clk3b_output()
403 	SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);  in store_enable_clk3a_output()
424 	SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);  in store_enable_clkb1_output()
446 	SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);  in store_enable_clka1_output()
467 	SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);  in store_enable_clkb0_output()
488 	SET_PORT_BITS(TLCLK_REG2, 0xfe, val);  in store_enable_clka0_output()
510 		SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);  in store_select_amcb2_transmit_clock()
511 		SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);  in store_select_amcb2_transmit_clock()
513 		SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);  in store_select_amcb2_transmit_clock()
516 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);  in store_select_amcb2_transmit_clock()
519 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);  in store_select_amcb2_transmit_clock()
522 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);  in store_select_amcb2_transmit_clock()
525 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);  in store_select_amcb2_transmit_clock()
529 		SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);  in store_select_amcb2_transmit_clock()
552 		SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);  in store_select_amcb1_transmit_clock()
553 		SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);  in store_select_amcb1_transmit_clock()
555 		SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);  in store_select_amcb1_transmit_clock()
558 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);  in store_select_amcb1_transmit_clock()
561 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);  in store_select_amcb1_transmit_clock()
564 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);  in store_select_amcb1_transmit_clock()
567 			SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);  in store_select_amcb1_transmit_clock()
571 		SET_PORT_BITS(TLCLK_REG3, 0xf8, val);  in store_select_amcb1_transmit_clock()
593 	SET_PORT_BITS(TLCLK_REG1, 0xfe, val);  in store_select_redundant_clock()
614 	SET_PORT_BITS(TLCLK_REG1, 0xfd, val);  in store_select_ref_frequency()
635 	SET_PORT_BITS(TLCLK_REG0, 0xfb, val);  in store_filter_select()
655 	SET_PORT_BITS(TLCLK_REG0, 0xbf, val);  in store_hardware_switching_mode()
676 	SET_PORT_BITS(TLCLK_REG0, 0x7f, val);  in store_hardware_switching()
694 	SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);  in store_refalign()
695 	SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);  in store_refalign()
696 	SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);  in store_refalign()
716 	SET_PORT_BITS(TLCLK_REG0, 0xcf, val);  in store_mode_select()
736 	SET_PORT_BITS(TLCLK_REG4, 0xfd, val);  in store_reset()
898 		SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);  in tlclk_interrupt()
910 		SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);  in tlclk_interrupt()