Lines Matching defs:_DSP_3780I_CONFIG_SETTINGS

264 typedef struct _DSP_3780I_CONFIG_SETTINGS {  struct
267 	unsigned short usBaseConfigIO;
270 	int bDSPEnabled;
271 	int bModemEnabled;
272 	int bInterruptClaimed;
275 	unsigned short usDspIrq;
276 	unsigned short usDspDma;
277 	unsigned short usDspBaseIO;
278 	unsigned short usUartIrq;
279 	unsigned short usUartBaseIO;
282 	int bDspIrqActiveLow;
283 	int bUartIrqActiveLow;
284 	int bDspIrqPulse;
285 	int bUartIrqPulse;
288 	unsigned uIps;
289 	unsigned uDStoreSize;
290 	unsigned uIStoreSize;
291 	unsigned uDmaBandwidth;
294 	unsigned short usNumTransfers;
295 	unsigned short usReRequest;
296 	int bEnableMEMCS16;
297 	unsigned short usIsaMemCmdWidth;
298 	int bGateIOCHRDY;
299 	int bEnablePwrMgmt;
300 	unsigned short usHBusTimerLoadValue;
301 	int bDisableLBusTimeout;
302 	unsigned short usN_Divisor;
303 	unsigned short usM_Multiplier;
304 	int bPllBypass;
305 	unsigned short usChipletEnable;	/* Used with the chip reset register to enable specific chiplets */
308 	int bUartSaved;		/* True after a successful save of the UART registers */
309 	unsigned char ucIER;	/* Interrupt enable register */
310 	unsigned char ucFCR;	/* FIFO control register */
311 	unsigned char ucLCR;	/* Line control register */
312 	unsigned char ucMCR;	/* Modem control register */
313 	unsigned char ucSCR;	/* Scratch register */
314 	unsigned char ucDLL;	/* Divisor latch, low byte */
315 	unsigned char ucDLM;	/* Divisor latch, high byte */