Lines Matching refs:intel_private
90 } intel_private; variable
92 #define INTEL_GTT_GEN intel_private.driver->gen
93 #define IS_G33 intel_private.driver->is_g33
94 #define IS_PINEVIEW intel_private.driver->is_pineview
95 #define IS_IRONLAKE intel_private.driver->is_ironlake
96 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
114 if (!dma_map_sg(&intel_private.pcidev->dev, st->sgl, st->nents, in intel_gtt_map_memory()
130 dma_unmap_sg(&intel_private.pcidev->dev, sg_list, num_sg, in intel_gtt_unmap_memory()
183 intel_private.i81x_gtt_table = gtt_table; in i810_setup()
185 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); in i810_setup()
187 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
188 if (!intel_private.registers) in i810_setup()
192 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
194 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; in i810_setup()
196 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
198 dev_info(&intel_private.pcidev->dev, in i810_setup()
200 intel_private.num_dcache_entries = 1024; in i810_setup()
208 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
209 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); in i810_cleanup()
219 > intel_private.num_dcache_entries) in i810_insert_dcache_entries()
227 intel_private.driver->write_entry(addr, in i810_insert_dcache_entries()
305 if (intel_private.needs_dmar) { in intel_gtt_setup_scratch_page()
306 dma_addr = dma_map_page(&intel_private.pcidev->dev, page, 0, in intel_gtt_setup_scratch_page()
308 if (dma_mapping_error(&intel_private.pcidev->dev, dma_addr)) { in intel_gtt_setup_scratch_page()
313 intel_private.scratch_page_dma = dma_addr; in intel_gtt_setup_scratch_page()
315 intel_private.scratch_page_dma = page_to_phys(page); in intel_gtt_setup_scratch_page()
317 intel_private.scratch_page = page; in intel_gtt_setup_scratch_page()
336 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); in i810_write_entry()
350 pci_read_config_word(intel_private.bridge_dev, in intel_gtt_stolen_size()
353 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || in intel_gtt_stolen_size()
354 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { in intel_gtt_stolen_size()
366 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
423 dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n", in intel_gtt_stolen_size()
426 dev_info(&intel_private.bridge_dev->dev, in intel_gtt_stolen_size()
439 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
441 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
444 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
447 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
456 pci_read_config_word(intel_private.bridge_dev, in i965_gtt_total_entries()
475 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_gtt_total_entries()
498 dev_info(&intel_private.pcidev->dev, in i965_gtt_total_entries()
514 return intel_private.gtt_mappable_entries; in intel_gtt_total_entries()
525 pci_read_config_dword(intel_private.bridge_dev, in intel_gtt_mappable_entries()
536 pci_read_config_word(intel_private.bridge_dev, in intel_gtt_mappable_entries()
545 aperture_size = pci_resource_len(intel_private.pcidev, 2); in intel_gtt_mappable_entries()
553 set_pages_wb(intel_private.scratch_page, 1); in intel_gtt_teardown_scratch_page()
554 if (intel_private.needs_dmar) in intel_gtt_teardown_scratch_page()
555 dma_unmap_page(&intel_private.pcidev->dev, in intel_gtt_teardown_scratch_page()
556 intel_private.scratch_page_dma, PAGE_SIZE, in intel_gtt_teardown_scratch_page()
558 __free_page(intel_private.scratch_page); in intel_gtt_teardown_scratch_page()
563 intel_private.driver->cleanup(); in intel_gtt_cleanup()
565 iounmap(intel_private.gtt); in intel_gtt_cleanup()
566 iounmap(intel_private.registers); in intel_gtt_cleanup()
576 const unsigned short gpu_devid = intel_private.pcidev->device; in needs_ilk_vtd_wa()
584 device_iommu_mapped(&intel_private.pcidev->dev)); in needs_ilk_vtd_wa()
607 ret = intel_private.driver->setup(); in intel_gtt_init()
611 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); in intel_gtt_init()
612 intel_private.gtt_total_entries = intel_gtt_total_entries(); in intel_gtt_init()
615 intel_private.PGETBL_save = in intel_gtt_init()
616 readl(intel_private.registers+I810_PGETBL_CTL) in intel_gtt_init()
620 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; in intel_gtt_init()
622 dev_info(&intel_private.bridge_dev->dev, in intel_gtt_init()
624 intel_private.gtt_total_entries * 4, in intel_gtt_init()
625 intel_private.gtt_mappable_entries * 4); in intel_gtt_init()
627 gtt_map_size = intel_private.gtt_total_entries * 4; in intel_gtt_init()
629 intel_private.gtt = NULL; in intel_gtt_init()
631 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, in intel_gtt_init()
633 if (intel_private.gtt == NULL) in intel_gtt_init()
634 intel_private.gtt = ioremap(intel_private.gtt_phys_addr, in intel_gtt_init()
636 if (intel_private.gtt == NULL) { in intel_gtt_init()
637 intel_private.driver->cleanup(); in intel_gtt_init()
638 iounmap(intel_private.registers); in intel_gtt_init()
646 intel_private.stolen_size = intel_gtt_stolen_size(); in intel_gtt_init()
648 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; in intel_gtt_init()
661 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); in intel_gtt_init()
680 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); in intel_fake_agp_fetch_size()
722 writel(readl(intel_private.registers+I830_HIC) | (1<<31), in i830_chipset_flush()
723 intel_private.registers+I830_HIC); in i830_chipset_flush()
725 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { in i830_chipset_flush()
741 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); in i830_write_entry()
751 pci_read_config_word(intel_private.bridge_dev, in intel_gmch_enable_gtt()
754 pci_write_config_word(intel_private.bridge_dev, in intel_gmch_enable_gtt()
757 pci_read_config_word(intel_private.bridge_dev, in intel_gmch_enable_gtt()
760 dev_err(&intel_private.pcidev->dev, in intel_gmch_enable_gtt()
771 writel(0, intel_private.registers+GFX_FLSH_CNTL); in intel_gmch_enable_gtt()
773 reg = intel_private.registers+I810_PGETBL_CTL; in intel_gmch_enable_gtt()
774 writel(intel_private.PGETBL_save, reg); in intel_gmch_enable_gtt()
776 dev_err(&intel_private.pcidev->dev, in intel_gmch_enable_gtt()
778 readl(reg), intel_private.PGETBL_save); in intel_gmch_enable_gtt()
783 writel(0, intel_private.registers+GFX_FLSH_CNTL); in intel_gmch_enable_gtt()
793 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); in i830_setup()
795 intel_private.registers = ioremap(reg_addr, KB(64)); in i830_setup()
796 if (!intel_private.registers) in i830_setup()
799 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; in i830_setup()
824 intel_private.clear_fake_agp = true; in intel_fake_agp_configure()
825 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; in intel_fake_agp_configure()
848 intel_private.driver->write_entry(addr, pg, flags); in intel_gmch_gtt_insert_page()
849 readl(intel_private.gtt + pg); in intel_gmch_gtt_insert_page()
850 if (intel_private.driver->chipset_flush) in intel_gmch_gtt_insert_page()
851 intel_private.driver->chipset_flush(); in intel_gmch_gtt_insert_page()
871 intel_private.driver->write_entry(addr, j, flags); in intel_gmch_gtt_insert_sg_entries()
875 readl(intel_private.gtt + j - 1); in intel_gmch_gtt_insert_sg_entries()
876 if (intel_private.driver->chipset_flush) in intel_gmch_gtt_insert_sg_entries()
877 intel_private.driver->chipset_flush(); in intel_gmch_gtt_insert_sg_entries()
891 intel_private.driver->write_entry(addr, in intel_gmch_gtt_insert_pages()
902 if (intel_private.clear_fake_agp) { in intel_fake_agp_insert_entries()
903 int start = intel_private.stolen_size / PAGE_SIZE; in intel_fake_agp_insert_entries()
904 int end = intel_private.gtt_mappable_entries; in intel_fake_agp_insert_entries()
906 intel_private.clear_fake_agp = false; in intel_fake_agp_insert_entries()
915 if (pg_start + mem->page_count > intel_private.gtt_total_entries) in intel_fake_agp_insert_entries()
921 if (!intel_private.driver->check_flags(type)) in intel_fake_agp_insert_entries()
927 if (intel_private.needs_dmar) { in intel_fake_agp_insert_entries()
954 intel_private.driver->write_entry(intel_private.scratch_page_dma, in intel_gmch_gtt_clear_range()
970 if (intel_private.needs_dmar) { in intel_fake_agp_remove_entries()
985 if (pg_count != intel_private.num_dcache_entries) in intel_fake_agp_alloc_by_type()
1008 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, in intel_alloc_chipset_flush_resource()
1010 pcibios_align_resource, intel_private.bridge_dev); in intel_alloc_chipset_flush_resource()
1020 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); in intel_i915_setup_chipset_flush()
1023 intel_private.resource_valid = 1; in intel_i915_setup_chipset_flush()
1024 …pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start &… in intel_i915_setup_chipset_flush()
1028 intel_private.resource_valid = 1; in intel_i915_setup_chipset_flush()
1029 intel_private.ifp_resource.start = temp; in intel_i915_setup_chipset_flush()
1030 intel_private.ifp_resource.end = temp + PAGE_SIZE; in intel_i915_setup_chipset_flush()
1031 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); in intel_i915_setup_chipset_flush()
1034 intel_private.resource_valid = 0; in intel_i915_setup_chipset_flush()
1043 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); in intel_i965_g33_setup_chipset_flush()
1044 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); in intel_i965_g33_setup_chipset_flush()
1050 intel_private.resource_valid = 1; in intel_i965_g33_setup_chipset_flush()
1051 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, in intel_i965_g33_setup_chipset_flush()
1052 upper_32_bits(intel_private.ifp_resource.start)); in intel_i965_g33_setup_chipset_flush()
1053 …pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start &… in intel_i965_g33_setup_chipset_flush()
1060 intel_private.resource_valid = 1; in intel_i965_g33_setup_chipset_flush()
1061 intel_private.ifp_resource.start = l64; in intel_i965_g33_setup_chipset_flush()
1062 intel_private.ifp_resource.end = l64 + PAGE_SIZE; in intel_i965_g33_setup_chipset_flush()
1063 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); in intel_i965_g33_setup_chipset_flush()
1066 intel_private.resource_valid = 0; in intel_i965_g33_setup_chipset_flush()
1073 if (intel_private.ifp_resource.start) in intel_i9xx_setup_flush()
1080 intel_private.ifp_resource.name = "Intel Flush Page"; in intel_i9xx_setup_flush()
1081 intel_private.ifp_resource.flags = IORESOURCE_MEM; in intel_i9xx_setup_flush()
1090 if (intel_private.ifp_resource.start) in intel_i9xx_setup_flush()
1091 intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE); in intel_i9xx_setup_flush()
1092 if (!intel_private.i9xx_flush_page) in intel_i9xx_setup_flush()
1093 dev_err(&intel_private.pcidev->dev, in intel_i9xx_setup_flush()
1099 if (intel_private.i9xx_flush_page) in i9xx_cleanup()
1100 iounmap(intel_private.i9xx_flush_page); in i9xx_cleanup()
1101 if (intel_private.resource_valid) in i9xx_cleanup()
1102 release_resource(&intel_private.ifp_resource); in i9xx_cleanup()
1103 intel_private.ifp_resource.start = 0; in i9xx_cleanup()
1104 intel_private.resource_valid = 0; in i9xx_cleanup()
1110 if (intel_private.i9xx_flush_page) in i9xx_chipset_flush()
1111 writel(1, intel_private.i9xx_flush_page); in i9xx_chipset_flush()
1126 writel_relaxed(addr | pte_flags, intel_private.gtt + entry); in i965_write_entry()
1134 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); in i9xx_setup()
1136 intel_private.registers = ioremap(reg_addr, size); in i9xx_setup()
1137 if (!intel_private.registers) in i9xx_setup()
1142 intel_private.gtt_phys_addr = in i9xx_setup()
1143 pci_resource_start(intel_private.pcidev, I915_PTE_BAR); in i9xx_setup()
1146 intel_private.gtt_phys_addr = reg_addr + MB(2); in i9xx_setup()
1149 intel_private.gtt_phys_addr = reg_addr + KB(512); in i9xx_setup()
1357 intel_private.pcidev = gmch_device; in find_gmch()
1370 intel_private.pcidev = pci_dev_get(gpu_pdev); in intel_gmch_probe()
1371 intel_private.driver = in intel_gmch_probe()
1377 intel_private.driver = in intel_gmch_probe()
1383 if (!intel_private.driver) in intel_gmch_probe()
1392 bridge->dev_private_data = &intel_private; in intel_gmch_probe()
1403 if (intel_private.refcount++) in intel_gmch_probe()
1406 intel_private.bridge_dev = pci_dev_get(bridge_pdev); in intel_gmch_probe()
1411 mask = intel_private.driver->dma_mask_size; in intel_gmch_probe()
1412 if (dma_set_mask(&intel_private.pcidev->dev, DMA_BIT_MASK(mask))) in intel_gmch_probe()
1413 dev_err(&intel_private.pcidev->dev, in intel_gmch_probe()
1417 dma_set_coherent_mask(&intel_private.pcidev->dev, in intel_gmch_probe()
1435 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; in intel_gmch_gtt_get()
1436 *mappable_base = intel_private.gma_bus_addr; in intel_gmch_gtt_get()
1437 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; in intel_gmch_gtt_get()
1443 if (intel_private.driver->chipset_flush) in intel_gmch_gtt_flush()
1444 intel_private.driver->chipset_flush(); in intel_gmch_gtt_flush()
1450 if (--intel_private.refcount) in intel_gmch_remove()
1453 if (intel_private.scratch_page) in intel_gmch_remove()
1455 if (intel_private.pcidev) in intel_gmch_remove()
1456 pci_dev_put(intel_private.pcidev); in intel_gmch_remove()
1457 if (intel_private.bridge_dev) in intel_gmch_remove()
1458 pci_dev_put(intel_private.bridge_dev); in intel_gmch_remove()
1459 intel_private.driver = NULL; in intel_gmch_remove()