103 	NV_ADMA_CTL			= 0x40,  enumerator
616 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
617 	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
646 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_mode()
647 	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_mode()
1028 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1030 		mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1031 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_freeze()
1046 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1048 		mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1049 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_thaw()
1173 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1175 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1177 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1178 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1179 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1181 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1182 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1192 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_stop()
1208 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_suspend()
1233 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1235 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1237 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1238 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1239 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1241 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1242 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1670 		tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1671 		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1672 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()
1674 		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1675 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()