Lines Matching defs:sata_dwc_regs
54 struct sata_dwc_regs { struct
55 u32 fptagr; /* 1st party DMA tag */
56 u32 fpbor; /* 1st party DMA buffer offset */
57 u32 fptcr; /* 1st party DMA Xfr count */
58 u32 dmacr; /* DMA Control */
59 u32 dbtsr; /* DMA Burst Transac size */
60 u32 intpr; /* Interrupt Pending */
61 u32 intmr; /* Interrupt Mask */
62 u32 errmr; /* Error Mask */
63 u32 llcr; /* Link Layer Control */
64 u32 phycr; /* PHY Control */
65 u32 physr; /* PHY Status */
66 u32 rxbistpd; /* Recvd BIST pattern def register */
67 u32 rxbistpd1; /* Recvd BIST data dword1 */
68 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
69 u32 txbistpd; /* Trans BIST pattern def register */
70 u32 txbistpd1; /* Trans BIST data dword1 */
71 u32 txbistpd2; /* Trans BIST data dword2 */
72 u32 bistcr; /* BIST Control Register */
73 u32 bistfctr; /* BIST FIS Count Register */
74 u32 bistsr; /* BIST Status Register */
75 u32 bistdecr; /* BIST Dword Error count register */
76 u32 res[15]; /* Reserved locations */
77 u32 testr; /* Test Register */
78 u32 versionr; /* Version Register */
79 u32 idr; /* ID Register */
80 u32 unimpl[192]; /* Unimplemented */
81 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
125 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */ member