drivers/ata/ahci_da850.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
51 	 * the refclk rate by ten.  in ahci_da850_calculate_mpy()
56 	WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10");  in ahci_da850_calculate_mpy()
86 		 * We should have divided evenly - if not, return an invalid  in ahci_da850_calculate_mpy()
108 	if (pmp && ret == -EBUSY)  in ahci_da850_softreset()
123 	 * we increased the PLL0 frequency to 456MHz from the default 300MHz.  in ahci_da850_hardreset()
133 	} while (retry--);  in ahci_da850_hardreset()
142 	 * No need to override .pmp_softreset - it's only used for actual
143 	 * PMP-enabled ports.
162 	struct device *dev = &pdev->dev;  in ahci_da850_probe()
178 	 * "refclk" id. If we haven't got all of them re-try the clocks  in ahci_da850_probe()
181 	if (hpriv->n_clks < 2) {  in ahci_da850_probe()
182 		hpriv->clks = devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL);  in ahci_da850_probe()
183 		if (!hpriv->clks)  in ahci_da850_probe()
184 			return -ENOMEM;  in ahci_da850_probe()
186 		hpriv->clks[0].id = "fck";  in ahci_da850_probe()
187 		hpriv->clks[1].id = "refclk";  in ahci_da850_probe()
188 		hpriv->n_clks = 2;  in ahci_da850_probe()
190 		rc = devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks);  in ahci_da850_probe()
195 	mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk));  in ahci_da850_probe()
197 		dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy);  in ahci_da850_probe()
198 		return -EINVAL;  in ahci_da850_probe()
207 		rc = -ENODEV;  in ahci_da850_probe()
211 	pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));  in ahci_da850_probe()
213 		rc = -ENOMEM;  in ahci_da850_probe()
217 	da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy);  in ahci_da850_probe()
234 	{ .compatible = "ti,da850-ahci", },