Lines Matching refs:u32
102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
106 static u32 pmc_atom_d3_mask = 0xfe000ffe;
132 u32 val; in lpss_uart_setup()
150 u32 val; in lpss_deassert_reset()
499 u32 flags;
730 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) in __lpss_reg_read()
735 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, in __lpss_reg_write()
741 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) in lpss_reg_read()
772 u32 ltr_value = 0; in lpss_ltr_show()
787 u32 ltr_mode = 0; in lpss_ltr_mode_show()
818 u32 ltr_mode, ltr_val; in acpi_lpss_set_ltr()
862 unsigned long offset = i * sizeof(u32); in acpi_lpss_save_ctx()
883 unsigned long offset = i * sizeof(u32); in acpi_lpss_restore_ctx()
961 u32 value1 = 0; in lpss_iosf_enter_d3_state()
962 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; in lpss_iosf_enter_d3_state()
963 u32 value2 = LPSS_PMCSR_D3hot; in lpss_iosf_enter_d3_state()
964 u32 mask2 = LPSS_PMCSR_Dx_MASK; in lpss_iosf_enter_d3_state()
970 u32 func_dis, d3_sts_0, pmc_status; in lpss_iosf_enter_d3_state()
1009 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | in lpss_iosf_exit_d3_state()
1011 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; in lpss_iosf_exit_d3_state()
1012 u32 value2 = LPSS_PMCSR_D0; in lpss_iosf_exit_d3_state()
1013 u32 mask2 = LPSS_PMCSR_Dx_MASK; in lpss_iosf_exit_d3_state()