189 #define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(VPU_37XX_HOST_MMU_GERROR, CMDQ)) | \
239 		return "Unknown CMDQ command";  in ivpu_mmu_event_to_str()
315 	struct ivpu_mmu_queue *q = &mmu->cmdq;  in ivpu_mmu_cmdq_alloc()
325 	ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n",  in ivpu_mmu_cmdq_alloc()
368 		ivpu_err(vdev, "Failed to allocate cmdq: %d\n", ret);  in ivpu_mmu_structs_alloc()
408 	struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq;  in ivpu_mmu_cmdq_wait_for_cons()  local
410 	return REGV_POLL(VPU_37XX_HOST_MMU_CMDQ_CONS, cmdq->cons, (cmdq->prod == cmdq->cons),  in ivpu_mmu_cmdq_wait_for_cons()
416 	struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;  in ivpu_mmu_cmdq_cmd_write()
436 	struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;  in ivpu_mmu_cmdq_sync()
488 	memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE);  in ivpu_mmu_reset()
489 	clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE);  in ivpu_mmu_reset()
490 	mmu->cmdq.prod = 0;  in ivpu_mmu_reset()
491 	mmu->cmdq.cons = 0;  in ivpu_mmu_reset()
512 	REGV_WR64(VPU_37XX_HOST_MMU_CMDQ_BASE, mmu->cmdq.dma_q);  in ivpu_mmu_reset()
858 		ivpu_warn_ratelimited(vdev, "MMU CMDQ MSI ABT write aborted\n");  in ivpu_mmu_irq_gerr_handler()
866 	if (REG_TEST_FLD(VPU_37XX_HOST_MMU_GERROR, CMDQ, active))  in ivpu_mmu_irq_gerr_handler()
867 		ivpu_err_ratelimited(vdev, "MMU CMDQ write aborted\n");  in ivpu_mmu_irq_gerr_handler()