270 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);  in ivpu_boot_host_ss_rst_drive()
287 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);  in ivpu_boot_host_ss_clk_drive()
304 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);  in ivpu_boot_noc_qreqn_check()
314 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);  in ivpu_boot_noc_qacceptn_check()
324 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);  in ivpu_boot_noc_qdeny_check()
334 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);  in ivpu_boot_top_noc_qrenqn_check()
345 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);  in ivpu_boot_top_noc_qacceptn_check()
356 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);  in ivpu_boot_top_noc_qdeny_check()
367 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);  in ivpu_boot_idle_gen_drive()
405 	val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);  in ivpu_boot_host_ss_axi_drive()
442 	val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);  in ivpu_boot_host_ss_top_noc_drive()
472 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);  in ivpu_boot_pwr_island_trickle_drive()
487 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);  in ivpu_boot_pwr_island_drive()
511 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);  in ivpu_boot_pwr_island_isolation_drive()
523 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);  in ivpu_boot_no_snoop_enable()
534 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);  in ivpu_boot_tbu_mmu_enable()
548 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);  in ivpu_boot_cpu_noc_qacceptn_check()
558 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);  in ivpu_boot_cpu_noc_qdeny_check()
603 	val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);  in ivpu_boot_soc_cpu_drive()
644 	val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);  in ivpu_boot_soc_cpu_boot()
923 	val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);  in ivpu_hw_40xx_wdt_disable()
964 	return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);  in ivpu_hw_40xx_reg_ipc_rx_addr_get()
1020 	u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;  in ivpu_hw_40xx_irqv_handler()
1135 	u32 irqv = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;  in ivpu_hw_40xx_diagnose_failure()