302 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);  in ivpu_boot_host_ss_rst_drive()
303 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);  in ivpu_boot_host_ss_rst_drive()
304 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);  in ivpu_boot_host_ss_rst_drive()
319 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);  in ivpu_boot_host_ss_clk_drive()
320 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);  in ivpu_boot_host_ss_clk_drive()
321 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);  in ivpu_boot_host_ss_clk_drive()
411 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);  in ivpu_boot_host_ss_axi_drive()
442 		val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val);  in ivpu_boot_host_ss_top_noc_drive()
443 		val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);  in ivpu_boot_host_ss_top_noc_drive()
472 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);  in ivpu_boot_pwr_island_trickle_drive()
484 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);  in ivpu_boot_pwr_island_drive()
506 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);  in ivpu_boot_pwr_island_isolation_drive()
518 		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);  in ivpu_boot_dpu_active_drive()
565 	val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);  in ivpu_boot_no_snoop_enable()
590 	val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val);  in ivpu_boot_soc_cpu_boot()
596 	val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);  in ivpu_boot_soc_cpu_boot()
624 		val = REG_CLR_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val);  in ivpu_boot_d0i3_drive()
798 	val = REG_CLR_FLD(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);  in ivpu_hw_37xx_wdt_disable()