89 	u32 gen_ctrl = REGV_RD32(VPU_37XX_HOST_SS_GEN_CTRL);  in ivpu_hw_read_platform()
295 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);  in ivpu_boot_host_ss_rst_drive()
312 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);  in ivpu_boot_host_ss_clk_drive()
329 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);  in ivpu_boot_noc_qreqn_check()
339 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);  in ivpu_boot_noc_qacceptn_check()
349 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);  in ivpu_boot_noc_qdeny_check()
359 	u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN);  in ivpu_boot_top_noc_qrenqn_check()
370 	u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QACCEPTN);  in ivpu_boot_top_noc_qacceptn_check()
381 	u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QDENY);  in ivpu_boot_top_noc_qdeny_check()
407 	val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);  in ivpu_boot_host_ss_axi_drive()
437 	val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN);  in ivpu_boot_host_ss_top_noc_drive()
467 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);  in ivpu_boot_pwr_island_trickle_drive()
479 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);  in ivpu_boot_pwr_island_drive()
501 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);  in ivpu_boot_pwr_island_isolation_drive()
513 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);  in ivpu_boot_dpu_active_drive()
562 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);  in ivpu_boot_no_snoop_enable()
573 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);  in ivpu_boot_tbu_mmu_enable()
587 	val = REGV_RD32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);  in ivpu_boot_soc_cpu_boot()
797 	val = REGV_RD32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG);  in ivpu_hw_37xx_wdt_disable()
854 	return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);  in ivpu_hw_37xx_reg_ipc_rx_addr_get()
915 	u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;  in ivpu_hw_37xx_irqv_handler()
1007 	u32 irqv = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK;  in ivpu_hw_37xx_diagnose_failure()